Static information storage and retrieval – Read/write circuit – Bad bit
Patent
1991-11-20
1993-01-12
Popek, Joseph A.
Static information storage and retrieval
Read/write circuit
Bad bit
371 102, G11C 700
Patent
active
051795361
ABSTRACT:
A semiconductor memory device comprises a first memory comprising memory cells for prestoring fixed data, a decoder for decoding an input address and for reading out a fixed data from the first memory based on a decoded input address, a second memory for storing a data identical to that prestored in a defective memory cell of the first memory, where the second memory comprising programmable non-volatile memory cells, a discriminating part including a third memory for storing a redundant address of each defective memory cell of the first memory for discriminating whether or not the input address coincides with the redundant address and for outputting a discrimination signal when the input address coincides with the redundant address, and a selecting part supplied with data read out from the first and second memories for normally outputting the data read out from the first memory and selectively outputting the data from the second memory when the discrimination signal is received from the discriminating part.
REFERENCES:
patent: 4376300 (1983-03-01), Tsang
patent: 4399372 (1983-08-01), Tanimoto et al.
patent: 4473895 (1984-09-01), Tatematsu
Araki Sunao
Arayama Yuji
Kasa Yasushi
Nagasawa Masanori
Takemae Yoshihiro
Fujitsu Limited
Fujitsu VLSI Limited
Popek Joseph A.
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