Semiconductor memory device having magnetoresistive elements

Details Semiconductor memory device having magnetoresistive elements Semiconductor memory device having magnetoresistive elements

2001-11-07

2003-02-18

Lam, David (Department: 2818)

Static information storage and retrieval

Systems using particular element

Magnetoresistive

C365S171000, C365S148000, C365S189011

Reexamination Certificate

active

06522575

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device having a non-volatile memory cell including a magnetoresistive element such as a GMR (giant magneto-resistance) element or a TMR (spin tunneling magneto-resistance) element.
1. Related Background Art
Up to now, there has been well known an SRAM (static random access memory) as a semiconductor memory device that enables the read/write of information at a high speed. Hereinafter, as a first conventional example of the semiconductor memory device, a memory cell of the SRAM will be described with reference to FIG.
6
.
FIG. 6
is a circuit diagram showing the structure of the memory cell of an SRAM which is a first conventional semiconductor memory device.
As shown in
FIG. 6
, the memory cell of the SRAM includes a first MOS transistor Q
11
and a second MOS transistor Q
12
whose sources are grounded and whose gates are connected to the mutual drains, a first load RL
1
inserted between the drain of the first MOS transistor Q
11
and a power source line, and a second load RL
2
inserted between the drain of the second MOS transistor
012
and the power source line.
The drain of the first MOS transistor Q
11
is connected with a first input/output terminal
11
, and the drain of the second MOS transistor Q
12
is connected with a second input/output terminal
12
.
In the above structure, when information is written in the memory cell shown in
FIG. 6
, different voltages are applied to the first input/output terminal
11
and the second input/output terminal
12
by a writing means not shown, respectively. In this example, in the case where the supply voltage to the first input/output terminal
11
is equal to or higher than a threshold voltage of the MOS transistor and the supply voltage to the second input/output terminal
12
is lower than the threshold voltage of the MOS transistor, the second MOS transistor Q
12
turns on to fix the potential of the second input/output terminal
12
to a ground potential GND, and the first MOS transistor Q
11
turns off to fix the potential of the first input/output terminal
11
to a power source potential Vcc.
On the contrary, in the case where the supply voltage to the first input/output terminal
11
is lower than the threshold voltage of the MOS transistor and the supply voltage to the second input/output terminal
12
is equal to or higher than the threshold voltage of the MOS transistor, the second MOS transistor Q
12
turns off to fix the potential of the second input/output terminal
12
to the power source potential Vcc, and the first MOS transistor Q
110
turns on to fix the potential of the first input/output terminal
11
to the ground potential GND.
Therefore, the information can be recorded as binary data depending on which potential of the first input/output terminal
11
or the second input/output terminal
12
being higher. This state is maintained so far as the power is supplied if new information is not written. Because the output potentials of the first input/output terminal
11
and the second input/output terminal
112
are amplified by the MOS transistor and fixed to the power source potential Vcc or the ground potential GND, a potential difference necessary to detect the information can be sufficiently ensured, thereby being capable of facilitating a process of reading the information by the read means not shown and also being capable of conducting the read/write operation at a high speed.
Subsequently, the memory cell including a magnetoresistive element such as a GMR element or a TMR element will be described as a second conventional semiconductor memory device with reference to the accompanying drawings.
FIG. 7
is a circuit diagram showing the structure of the memory cell having a magnetoresistive element which is the second conventional semiconductor memory device.
As shown in
FIG. 7
, the second conventional memory cell includes a first magnetoresistive element R
21
and a second magnetoresistive element R
22
whose one terminals are grounded, respectively, a first MOS transistor Q
21
inserted between the other terminal of the first magnetoresistive element R
21
and a current supply line, and a second MOS transistor Q
22
inserted between the other terminal of the second magnetoresistive element R
22
and the current supply line.
The drains of the first MOS transistor Q
21
and the second MOS transistor Q
22
are connected to the current supply line, respectively, the source of the first MOS transistor Q
21
is connected to the other terminal of the first magnetoresistive element R
21
, and the source of the second MOS transistor Q
22
is connected to the other terminal of the second magnetoresistive element R
22
. Also, the gates of the first MOS transistor Q
21
and the second MOS transistor Q
22
are connected commonly to a control terminal
21
, respectively.
The first magnetoresistive element R
21
and the second magnetoresistive element R
22
are formed of a GMR element or a TMR element and are so structured as to have two magnetic layers different in coercive force, respectively, and a non-magnetic layer intervened therebetween. The first magnetoresistive element R
21
and the second magnetoresistive element R
22
are elements exhibiting different resistances depending on the magnetizing direction of those two magnetic,layers being in the same direction or in opposite direction.
A first write line
22
for controlling the magnetizing direction of the magnetic layer of the first magnetoresistive element R
21
is disposed at a position that is close to the first magnetoresistive element R
21
, and a second write line
23
for controlling the magnetizing direction of the magnetic layer of the rsecond magnetoresistive element R
22
is disposed at a position that is close to the second magnetoresistive element R
22
.
In this structure, when information is written in the memory cell shown in
FIG. 7
, write currents are allowed to flow in the first write line
22
and the second write line
23
in opposite directions by the write means not shown, and the magnetic layers are magnetized by a magnetic field developed around the write line so that the resistances of the first magnetoresistive element R
21
and the second magnetoresistive element R
22
are different from each other.
The information can be recorded as binary data depending on which resistance of the first magnetoresistive element R
21
and the second magnetoresistive element R
22
being larger. Because the resistances of the first magnetoresistive element R
21
and the second magnetoresistive element R
22
are not. changed even if the power source turns off unless new information is written in those elements, respectively, the memory cell shown in
FIG. 7
functions as the non-volatile memory cell.
On the other hand, when the information is read from the memory cell shown in
FIG. 7
, a given voltage is applied to the control terminal
21
by a read means not shown, the first MOS transistor Q
21
and the second MOS transistor Q
22
are turned on to apply the same voltage to the first magnetoresistive element R
21
and the second magnetoresistive element R
22
, respectively. In this situation, because currents corresponding to the respective resistances flow in the first magnetoresistive element R
21
and the second magnetoresistive element R
22
, respectively, and a current difference occurs between a current I
21
that flows in the first magnetoresistive element R
21
and a current I
22
that flows in the second magnetoresistive element, the written information can be read by detecting the current difference by the read means.
However, among the above-mentioned conventional semiconductor memory devices, because the memory cell of the first conventional SRAM is the volatile memory cell, the information written at the same time when the power source turns off disappears. On the other hand, in the memory cell having the second conventional magnetoresistive element, because the information is rewritten by changing the magnetizing dir

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