Semiconductor memory device having level converters

Details Semiconductor memory device having level converters Semiconductor memory device having level converters

1988-10-24

1990-01-09

Fears, Terrell W.

Static information storage and retrieval

Read/write circuit

Simultaneous operations

36523006, G11C 1300

Patent

active

048932744

ABSTRACT:
A semiconductor memory device including a plurality of level converters, each of the level converters including a bridge circuit constituted by four MOS transistors having one type of conductivity, gates of one pair of four transistors opposing each other receiving a first signal and gates of the other pair of four transistors opposing each other receiving a signal complementary to the first signal; a pair of complementary MOS inverter circuits to which a second signal and a signal complementary to the second signal are input, respectively, the outputs of the pair of inverter circuits being connected to a first pair of connecting points positioned alternately in the bridge circuit, respectively; and a flip-flop circuit connected between a second pair of connecting points positioned alternately in the bridge circuit, to thereby output a third signal and a signal complementary to the third signal from the second pair of connecting points, resepctively.

REFERENCES:
patent: 4686650 (1987-08-01), Hori et al.

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