Semiconductor memory device having internal timing generator sha

Details Semiconductor memory device having internal timing generator sha Semiconductor memory device having internal timing generator sha

1998-04-23

2000-03-14

Nelms, David

Static information storage and retrieval

Read/write circuit

Serial read/write

3652385, G11C 700

Patent

active

060381841

ABSTRACT:
A semiconductor dynamic random access memory device serially reads out data bits from and serially writes data bits into memory cells through a long burst cycle, and the data bits are transferred between a read/write data bus to data latch circuits, between the data latch circuits and the main/sub sense amplifiers and the main/sub sense amplifiers and the sub-bit line pairs; while the data bits are being stepwise transferred between the memory cells and the read/write data bus, an internal timing controller not only provides activation timings and deactivation timings to the main-sub sense amplifiers and transfer gate arrays but also the starting point and the end point of the long burst cycle so that the semiconductor dynamic random access memory device is fabricated on a relatively small semiconductor chip.

REFERENCES:
patent: 4947373 (1990-08-01), Yamaguchi et al.
patent: 5381367 (1995-01-01), Kajimoto
"The fundmentals of digital data circuits", published May 15, 1986, Technology Reviews Co. Ltd., pp. 146-147, Doctor Tadashi Miyamoto.

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