Semiconductor memory device having internal data read...

Details Semiconductor memory device having internal data read... Semiconductor memory device having internal data read...

2001-07-18

2002-10-08

Elms, Richard (Department: 2824)

Static information storage and retrieval

Read/write circuit

Flip-flop used for sensing

C365S206000, C365S207000

Reexamination Certificate

active

06462999

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a configuration of a portion for reading of internal data in a semiconductor memory device. More particularly, the present invention relates to a sense amplifier circuit for internally amplifying data of a selected memory cell.
2. Description of the Background Art
FIG. 9
shows an exemplary configuration of a memory cell in a conventional static random access memory (SRAM). Referring to
FIG. 9
, the memory cell MC includes: a P channel MOS transistor (insulated gate type field effect transistor) MP
01
connected between a power supply node and a storage node NDA and having its gate connected to a storage node NDB; a P channel MOS transistor MP
02
connected between a power supply node and storage node NDB and having its gate connected to storage node NDA; an N channel MOS transistor MN
03
connected between storage node NDA and a ground node and having its gate connected to storage node NDB; an N channel MOS transistor MN
04
connected between storage node NDB and a ground node and having its gate connected to storage node NDA; an N channel MOS transistor MN
05
rendered conductive selectively in response to a signal potential on a word line WL to connect storage node NDA to a bit line BL; and an N channel MOS transistor MN
06
rendered conductive selectively in response to the signal potential on the word line WL to connect storage node NDB to a bit line /BL.
MOS transistors MP
01
and MN
03
constitute a CMOS inverter circuit, and MOS transistors MP
02
and MN
04
constitute another CMOS inverter circuit. These CMOS inverter circuits have their inputs and outputs cross-coupled to each other, thereby constituting a flip-flop. Storage nodes NDA and NDB latch data complementary with each other.
In access to memory cell MC (for data writing/reading), word line WL is driven to a selected state, and its voltage level attains an H level. In response, MOS transistors MN
05
and MN
06
are rendered conductive, and storage nodes NDA and NDB are connected to bit lines BL and /BL, respectively. In data reading, a voltage difference occurs between bit lines BL and /BL according to the voltages on storage nodes NDA and NDB. The voltage difference is sensed to be read in the data reading.
In data writing, complementary write data are transmitted to bit lines BL and /BL. The voltage levels of storage nodes NDA and NDB are set according to the write data.
In the configuration of SRAM cell MC shown in
FIG. 9
, load transistors MP
01
and MP
02
for retaining data of an H level are each formed, e.g., of a thin film transistor (TFT), which allows reduction in occupying area compared to the case where a pure resistance element is utilized for the load element. These load transistors (P channel MOS transistors) MP
01
and MP
02
have equivalent resistance values in the non-conductive states significantly greater than those in the conductive states. Thus, compared to the case where the pure resistance element is utilized as the load element, a through current and hence, current consumption during retaining data, can be reduced.
FIG. 10
schematically shows a configuration of a portion related to data reading in a conventional SRAM. Referring to
FIG. 10
, memory cells MC are arranged in rows and columns. Each memory cell MC has a configuration as shown in FIG.
9
. Word lines WL
0
, WL
1
, . . . are placed corresponding to respective rows of memory cells MC, and bit line pairs BL
0
, /BL
0
; BL
1
, /BL
1
, . . . are placed corresponding to respective columns of memory cells MC. Bit line precharge/equalize circuits BPE
0
, BPE
1
are provided for bit line pairs BL
0
and /BL
0
, BL
1
and /BL
1
, respectively, for precharging and equalizing the corresponding bit line pairs BL
0
and /BL
0
; BL
1
and /BL
1
to a power supply voltage VDD level in response to a precharge/equalize instructing signal /BLEQ.
Column select gates CSG
0
, CSG
1
are provided for bit line pairs BL
0
and /BL
0
, BL
1
and /BL
1
, respectively, which connect the corresponding bit line pair to an internal data line pair IOP according to column select signals on column select lines CSL
0
, CSL
1
, respectively. Column select gate CSG
0
includes a CMOS transmission gate TX
00
provided for bit line BL
0
and a CMOS transmission gate TX
01
provided for bit line /BL
0
, and is rendered conductive in response to the column select signal on column select line CSL
0
and an output signal of an inverter IVa receiving this column select signal. Each of CMOS transmission gates TX
00
and TX
01
includes a P channel MOS transistor PQ and an N channel MOS transistor NQ that are connected in parallel with each other.
Column select gate CSG
1
includes a CMOS transmission gate TX
10
provided for bit line BL
1
and a CMOS transmission gate TX
11
provided for bit line /BL
1
, and is rendered conductive in response to the column select signal on column select line CSLL and an output signal of an inverter IVb receiving this column select signal.
One bit line pair is selected by the column select signals on the column select lines, and the selected bit line pair is connected via the corresponding column select gate to internal data line pair IOP.
For internal data line pair IOP, there are provided a data line precharge/equalize circuit IPE that is responsive to activation of precharge/equalize instructing signal /BLEQ for precharging and equalizing internal data line pair IOP to a power supply voltage level, and a sense amplifier
100
that is responsive to activation of a sense amplifier activating signal SAE for differentially amplifying the signals on internal data line pair IOP to generate internal read data Dout and /Dout. Specifically, sense amplifier
100
, when activated, differentially amplifies a voltage difference, appearing on internal data line pair IOP, corresponding to data of a selected memory cell, and generates complementary internal read data Dout and /Dout. The detailed configuration of sense amplifier
100
will be described later.
In the SRAM shown in
FIG. 10
, in the stand-by state, bit line precharge/equalize circuits BPE
0
, BPE
1
, . . . and data line precharge/equalize circuit IPE are in an active state. Bite line pairs BL
0
, /BL
0
; /BL
1
, /BL
1
, . . . are held at a power supply voltage level, and internal data line pair IOP is precharged and equalized to the power supply voltage level.
When a data access cycle for data writing/reading starts, a word line corresponding to an addressed row is driven to a selected state, and storage data in the memory cells connected to the selected word line are read out to the corresponding bit line pairs. Memory cells MC each have a configuration as shown in
FIG. 9
, so that complementary data on bit lines BL and /BL are read out to the corresponding bit line pairs. In the data reading, bit line precharge/equalize circuits BPE
0
, BPE
1
, . . . are in an inactive state. Thus, voltage differences according to the storage data in the selected memory cells (memory cells connected to the selected word line) are generated in the respective bit line pairs.
Further, the column select line corresponding to an addressed column is driven to a selected state, and column select gate CSG connected to this selected column select line is rendered conductive. The bit line pair corresponding to the selected column is connected to internal data line pair IOP, and the voltage difference corresponding to the storage data in the selected memory cell is generated on this internal data line pair IOP. Here, data line precharge/equalize circuit IPE is already driven to an inactive state upon entering the access cycle.
Sense amplifier
100
differentially amplifies this voltage difference of internal data line pair IOP to generate internal read data Dout and /Dout.
FIG. 11
shows, by way of example, specific configurations of bit line precharge/equalize circuits BPE
0
, IPE and sense amplifier
100
shown in FIG.
10
. In
FIG. 11
, one bit line pair BL#, /BL# is shown representatively.
Bit line prechar

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