Semiconductor memory device having input first-stage circuit

Static information storage and retrieval – Read/write circuit – Noise suppression

Reexamination Certificate

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Details

C365S189090, C365S210100, C327S077000

Reexamination Certificate

active

07889584

ABSTRACT:
A semiconductor memory device of the present invention determines a logic level of a signal based on a predetermined reference voltage. And the memory device has an input terminal to which a reference signal having the reference voltage is input, a low-pass filter connected to the input terminal for passing a component of the reference voltage of the reference signal and eliminating undesired high frequency components, and one or more input first-stage circuits to each of which an output of the low-pass filter and a signal having the logic level to be determined are connected. In the memory device, the low-pass filter has predetermined attenuation at least at a frequency of an operating clock.

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Japanese Office Action issued in Japanese Patent Application No. 2005-300803, mailed Jul. 13, 2010.

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