Static information storage and retrieval – Read/write circuit – Bad bit
Patent
1985-12-24
1988-10-25
Popek, Joseph A.
Static information storage and retrieval
Read/write circuit
Bad bit
G11C 700
Patent
active
047808519
ABSTRACT:
A memory device provided with a redundant scheme in which a leakage current and unnecessary power consumption due to defective memory cells are suppressed is disclosed. The memory device has an array of memory cells which are divided into a plurality of sections, and a branch power supply line is provided between each section and adapted to be connected to a common power supply line, the branch power supply line for a defective section including defective memory cell being cut to electrically isolate the defective section from the common power supply line.
REFERENCES:
patent: 4546455 (1985-10-01), Iwahashi et al.
patent: 4639895 (1987-01-01), Iwahashi et al.
P. W. Cook et al., "Memory System Fabrication Using Laser Formed Connections", IBM Technical Disclosure Bulletin, vol. 17, No. 1, June 1974, pp. 245-247.
NEC Corporation
Popek Joseph A.
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