Semiconductor memory device having improved redundant structure

Static information storage and retrieval – Read/write circuit – Bad bit

Patent

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

G11C 700

Patent

active

047808519

ABSTRACT:
A memory device provided with a redundant scheme in which a leakage current and unnecessary power consumption due to defective memory cells are suppressed is disclosed. The memory device has an array of memory cells which are divided into a plurality of sections, and a branch power supply line is provided between each section and adapted to be connected to a common power supply line, the branch power supply line for a defective section including defective memory cell being cut to electrically isolate the defective section from the common power supply line.

REFERENCES:
patent: 4546455 (1985-10-01), Iwahashi et al.
patent: 4639895 (1987-01-01), Iwahashi et al.
P. W. Cook et al., "Memory System Fabrication Using Laser Formed Connections", IBM Technical Disclosure Bulletin, vol. 17, No. 1, June 1974, pp. 245-247.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Semiconductor memory device having improved redundant structure does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor memory device having improved redundant structure, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor memory device having improved redundant structure will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-2273502

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.