Static information storage and retrieval – Read/write circuit – Flip-flop used for sensing
Patent
1997-04-18
1999-08-31
Nguyen, Viet Q.
Static information storage and retrieval
Read/write circuit
Flip-flop used for sensing
36518901, 365207, 365190, G11C 700
Patent
active
059462523
ABSTRACT:
Segment data line pairs connected to a bit line pair are separated into segment data line pair for reading, and segment data line pair for writing. Global data line pairs connected to segment data line pair are separated into global data line pair for reading and global data line pair for writing. Connection between bit line pair and segment data line pair for reading is provided through a first read amplifier, while segment data line pair for reading is connected to global data line pair for reading through a second read amplifier. The first read amplifier includes two MOS transistors connected in series between one of the segment data line pair for reading and the ground power supply, and two MOS transistors connected in series between the other one of the segment data line pair for reading and the ground power supply. The second read amplifier includes two MOS transistors connected in series between one of the global data line pair for writing and the ground power supply, and two MOS transistors connected in series between the other one of the global data line pair for writing and the ground power supply.
REFERENCES:
patent: 5193076 (1993-03-01), Houston
patent: 5293343 (1994-03-01), Raab et al.
patent: 5333121 (1994-07-01), Geib
patent: 5392242 (1995-02-01), Koike
patent: 5436910 (1995-07-01), Takeshima et al.
patent: 5452252 (1995-09-01), Wada
patent: 5500820 (1996-03-01), Nakaoka
patent: 5521878 (1996-05-01), Ohtami et al.
patent: 5610871 (1997-03-01), Hidaka
patent: 5657275 (1997-08-01), Yoshida
patent: 5657286 (1997-08-01), Arimoto
patent: 5701269 (1997-12-01), Fujii
patent: 5828594 (1998-10-01), Fujii
"A 40NS 64MB DRAM with Current-Sensing Data-Bus Amplifier", Masao Taguchi et al., Feb. 1991, IEEE International Solid-State Circuits Conference, pp. 112-113.
"A LSV Circuit Technology for 64MB DRAMs", Y. Nakagome et al., 1990 Symposium on VLSI Circuits, pp. 17-18.
Mitsubishi Denki & Kabushiki Kaisha
Nguyen Viet Q.
LandOfFree
Semiconductor memory device having improved manner of data line does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor memory device having improved manner of data line , we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor memory device having improved manner of data line will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2427962