Semiconductor memory device having improved bit line distributio

Details Semiconductor memory device having improved bit line distributio Semiconductor memory device having improved bit line distributio

1996-12-18

1997-11-25

Dinh, Son T.

Static information storage and retrieval

Interconnection arrangements

365 51, 365149, 36523003, G11C 506

Patent

active

056919336

ABSTRACT:
A dynamic-type semiconductor memory including a memory cell array having a first, a second, a third and a fourth pair of bit lines which are arranged in parallel. A first sense amplifier circuit is arranged contiguous to one side of the memory cell array and is coupled to the first pair of bit lines. A second and a third sense amplifier circuit are arranged contiguous to the other side of the memory cell array and are coupled respectively to the second and the third pair of bit lines. A fourth sense amplifier circuit is arranged contiguous to the same side of the memory cell array as the first sense amplifier circuit and is coupled to the fourth pair of bit lines. In a preferred embodiment, a first signal line is connected to a second signal line at a region bounded by the ends of the second and the third bit line pairs and the first and the fourth sense amplifier circuits, thereby achieving low resistance for the equalizing signal lines, while maintaining a bit line arrangement of a mostly packed structure.

REFERENCES:
patent: 4903344 (1990-02-01), Inoue
patent: 5014241 (1991-05-01), Asakura et al.
patent: 5272665 (1993-12-01), Uesugi
patent: 5383159 (1995-01-01), Kubota
Masato Matsumiya, et al., "A 15-ns 16-Mb CMOS SRAM with Interdigitated Bit-Line Architecture", IEEE Journal of Solid-State Circuits, vol. 27, No. 11, Nov. 1992.

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