Semiconductor memory device having improved arrangement for...

Details Semiconductor memory device having improved arrangement for... Semiconductor memory device having improved arrangement for...

2005-06-21

2005-06-21

Yoha, Connie C. (Department: 2818)

Static information storage and retrieval

Read/write circuit

Bad bit

C365S230030, C365S189070, C365S225700

Reexamination Certificate

active

06909646

ABSTRACT:
In a bit-line direction, a plurality of memory mats are arranged including a plurality of memory cells respectively coupled to bit lines and word lines, and a sense amplifier array is arranged including a plurality of latch circuits having input/output nodes connected to a half of bit-line pairs separately provided to the memory mats in a region between the memory mats placed in the bit-line direction, thereby making possible to replace with a redundant bit line pair and the corresponding redundant sense amplifier on a basis of each bit-line pair and sense amplifier connected thereto, thereby realizing effective and rational Y-system relief.

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Micropatent PatSearch—Abstract of JP 07-296328.
S. Narumi et al., “Simulation of the write filed for T-shaped pole heads”, Journal of Applied Physics, vol. 87, No. 9, Parts 2 and 3, May 1, 2000.

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