Semiconductor memory device having high speed sense amplifier

Static information storage and retrieval – Read/write circuit – Differential sensing

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Details

365208, 327 52, G11C 702

Patent

active

055285449

ABSTRACT:
Disclosed herein is a semiconductor memory device comprising an N-channel transistor and a P-channel transistor Q33 which are provided in parallel between a sense node and a power supply line, The N-channel transistor has a threshold value of near 0 V and a specified current drive capability. The P-channel transistor Q33 charges the sense node up to the level that is smaller than a power supply voltage by a threshold value thereof and the level at the sense node is then changed by use of the N-channel transistor in accordance with data stored in the memory cell coupled to the sense node.

REFERENCES:
patent: 5029138 (1991-07-01), Iwashita
patent: 5056063 (1991-10-01), Santin et al.
patent: 5198997 (1993-03-01), Arakawa
patent: 5206552 (1993-04-01), Iwashita

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