Semiconductor memory device having high-speed input/output...

Details Semiconductor memory device having high-speed input/output... Semiconductor memory device having high-speed input/output...

2005-06-21

2005-06-21

Hoang, Huan (Department: 2827)

Static information storage and retrieval

Addressing

Sync/clocking

C365S230040, C365S230060

Reexamination Certificate

active

06909665

ABSTRACT:
A frequency divider divides the external clock signal by two and generates a first clock signal for an even-numbered data patch and a second clock signal for an odd-numbered data, wherein the first clock signal is opposite in phase to the second clock signal. A column selection line enable control circuit generates even-numbered column selection line enable signals in response to the first clock signal and generates odd-numbered column selection line enable signals in response to the second clock signal. A switching circuit connects a pair of bit lines to a pair of even-numbered input/output (I/O) lines in response to the even-numbered column selection line enable signals and connects the pair of bit lines to a pair of odd-numbered I/O lines in response to the odd-numbered column selection line enable signals. An I/O line sense amplification circuit senses and amplifies even-numbered read data from the pair of even-numbered I/O lines and outputs the amplified even-numbered read data to a pair of data lines in response to the first clock signal, and senses and amplifies odd-numbered read data from the pair of odd-numbered I/O lines and outputs the odd-numbered read data to the pair of data lines in response to the second clock signal.

REFERENCES:
patent: 5237532 (1993-08-01), Sahara et al.
patent: 5640358 (1997-06-01), Monden
patent: 5708623 (1998-01-01), Choi

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