Semiconductor memory device having high capacitance and improved

Static information storage and retrieval – Systems using particular element – Semiconductive

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365149, 357 236, 357 41, G11C 1134, G11C 1124, H01L 2978, H01L 2702

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048336475

ABSTRACT:
The semiconductor memory device of the present invention is formed on an integrated substrate and is immune to alpha radiation. The device includes a semiconductor substrate of a first conductive type and a memory cell formed in the substrate which has a switching MOS transistor having at least a first impurity region of a second conductive type and a capacitor connected to the transistor for storing memory data. A second impurity region of the first conductive type and having a higher concentration than that of the substrate is provided on the substrate surface at a position covering the first impurity region.

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patent: 4355374 (1982-10-01), Sakai et al.
patent: 4482908 (1984-11-01), Henderson, Sr.
patent: 4538166 (1985-08-01), Nakano
Rideout, V. L., IBM Technical Disclosure Bulletin, vol. 21, No. 9, Feb. 1979 , "Double Polysilicon Dynamic RAM Cell With Increased Charge Stage Capacitance" pp. 3823-3825.
IBM Technical Disclosure Bulletin, vol. 27, No. 7B, Dec. 1984, pp. 4463; 4464.
IBM Technical Disclosure Bulletin, vol. 26, No. 5, Oct. 1983, pp. 2597-2599.
Patents Abstracts of Japan, vol. 5, No. 34 (E-48) [706], Mar. 4, 1981.
Patents Abstracts of Japan, vol. 7, No. 40 (E-159) [1185], Feb. 17, 1983.
Patents Abstracts of Japan, vol. 9, No. 266 (E-352) [1989], Oct. 23, 1985.
The HI-C Ram Cell Concept-Al F. Tasch, Member, IEEE Jr., et al. pp. 33-41.

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