Semiconductor memory device having hierarchical wordline...

Details Semiconductor memory device having hierarchical wordline... Semiconductor memory device having hierarchical wordline...

2001-01-05

2002-12-10

Nguyen, Viet Q. (Department: 2818)

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

C365S230010, C365S230030, C365S227000

Reexamination Certificate

active

06493284

ABSTRACT:

This application relies for priority upon Korean Patent Application No. 2000-00303, filed on Jan. 5, 2000, the contents of which are herein incorporated by reference in their entirety.
FIELD OF THE INVENTION
The present invention relates to semiconductor integrated circuits, and more particularly to a random access memory device constructed with divided, or hierarchical, wordlines.
BACKGROUND OF THE INVENTION
A plurality of wordlines arranged in a semiconductor memory is conducted under the control of row decoders. A smaller space resulting from higher integration of the memory device makes it difficult to layout one decoder unit for one wordline. For this reason, in most semiconductor memory devices, there have recently been used a hierarchical wordline structure where a plurality of hierarchical wordline drive circuits share one output of the row decoder and are incorporated with sub-row decoders to select last one of the wordlines.
The hierarchical wordline structure is exemplarily disclosed in U.S. Pat. No. 5,764,585 entitled “SEMICONDUCTOR MEMORY DEVICE HAVING MAIN WORDLINES AND SUB-WORDLINE”; U.S. Pat. No. 5,875,149 entitled “WORDLINE DRIVER FOR SEMICONDUCTOR MEMORIES”, U.S. Pat. No. 5,862,098 entitled “WORDLINE DRIVER CIRCUIT FOR SEMICONDUCTOR MEMORY DEVICE”, U.S. Pat. No. 5,933,388 entitled “SUB-ROW DECODER CIRCUIT FOR SEMICONDUCTOR MEMORY DEVICE”, and U.S. Pat. No. 5,943,289 entitled “HIERARCHICAL WORDLINE STRUCTURE”.
Referring to prior art
FIG. 1
, a semiconductor memory device formed on a semiconductor chip
1
includes four memory blocks, also referred to as array blocks, MB
1
, MB
2
, MB
3
, and MB
4
. Each of MB
1
, MB
2
, MB
3
, and MB
4
includes a plurality of memory cells. In a 4-bit structure, a 1-bit memory cell is selected in each of MB
1
, MB
2
, MB
3
, and MB
4
during a normal operation. And then, data is written/read out to/from the selected memory cell. Predecoders, input buffers, and output buffers are arranged in peripheral circuitry that is located in a center of the semiconductor chip
1
. That is, the peripheral circuitry is located in the regions spaced between blocks MB
1
and MB
3
, and MB
2
and MB
4
.
Each of the memory blocks MB
1
, MB
2
, MB
3
, and MB
4
is composed of one or more sub-array blocks each including memory cells in which rows and columns are arranged, sub-wordlines arranged along the rows, and bitlines arranged along the columns. In
FIG. 2
, one of sub-array blocks is schematically illustrated. Three sub-wordline drive units (SWD)
10
,
12
, and
14
and two sub-arrays
16
and
18
are provided to a sub-array block. The sub-array
16
is arranged between the sub-wordline drive units
10
and
12
. And, the sub-array
18
is arranged between sub-wordline drive units
12
and
14
.
In the sub-array
16
, only four sub-wordlines SWL
0
, SWL
1
, SWL
2
, and SWL
3
corresponding to one main wordline MWL
0
are illustrated. SWL
0
and SWL
2
of the sub-array
16
are coupled to the sub-wordline drive unit
12
. SWL
1
and SWL
3
of the sub-array
16
are coupled to the sub-wordline drive unit
10
. Similarly, SWL
0
and SWL
2
of the sub-array
18
are coupled to the sub-wordline drive unit
12
. SWL
1
and SWL
3
of the sub-array
18
are coupled to the sub-wordline drive unit
14
. A sub-wordline drivers
20
, corresponding to sub-wordlines respectively, are provided to the sub-wordline drive units
10
,
12
, and
14
. The sub-wordline drivers
20
are commonly coupled to one main wordline MWL
0
.
With reference to
FIG. 2
, through a driver
22
a,
a sub-wordline activation signal, also referred to as “sub-wordline booting signal”, PX
0
is applied to one of two sub-wordline drivers
20
that are provided to the sub-wordline drive unit
10
. Through a driver
22
b,
a sub-wordline activation signal PX
2
is applied to the other driver
20
. Through the driver
22
a,
a sub-wordline activation signal PX
1
is applied to one of two sub-wordline drivers
20
that are provided to the sub-wordline drive unit
12
. Through the driver
22
b,
a sub-wordline activation signal PX
3
is applied to the other driver
20
. Through the driver
22
a,
PX
0
is applied to one of two drivers
20
that are provided to the sub-wordline drive unit
14
. Through the driver
22
b,
PX
2
is applied to the other drivers
20
.
The sub-wordline activation signals PX
0
, PX
1
, PX
2
, and PX
3
are generated by the above-described sub-row decoders PXi (not shown), and have high level of a boosting voltage, Vpp, that is higher than a power supply voltage. During a normal operation, only one of the sub-wordline activation signals PXi has high level. As shown in
FIG. 2
, sense amplifiers are provided between areas referred to as “conjunction regions”
24
in which the drivers
22
a
and
22
b
are arranged. And, bitlines arranged in corresponding sub-arrays
16
and
18
are coupled therebetween. It is understood to those skilled in the art that the sense amplifiers are shared by adjacent sub-array (not shown). Other sub-array blocks provided to each of the memory blocks MB
1
, MB
2
, MB
3
, and MB
4
are composed same as shown in FIG.
2
.
To select a memory cell MC, designated by the box of broken lines, of the sub-array
16
that is arranged between the sub-wordline drive units
10
and
12
, a main wordline MWL
0
is selected and a sub-wordline activation signal PX
2
has high level of a boosting voltage. At this time, other signals PX
0
, PX
1
, and PX
3
have low level of a ground voltage. Other memory cells associated with the main wordline MWL
0
can be selected using the same manner as described above.
Based upon such an arrangement of the sub-wordline activation signals PXi (i=0-1), power, especially boosting voltage Vpp, consumed in selecting the sub-wordline activation signal differs for each signal, resulting in power consumption imbalance on one signal. This has an influence on circuit operations such as noise, operation speed, and signal skew, among others. More specifically, a sub-wordline activation signal PX
0
or PX
2
is provided to two sub-wordline drive units
10
and
14
through corresponding drivers, and sub-wordline activation signal PX
1
or PX
3
is provided to only one sub-wordline drive unit
12
through corresponding drivers, as shown in FIG.
2
. Loading of a signal line transferring PX
0
or PX
2
is greater than that of a signal line transferring PX
1
or PX
3
. Therefore, associated with MB
1
, MB
2
, MB
3
, and MB
4
, power consumed in selecting PX
0
or PX
2
is greater than that in electing PX
1
or PX
3
(see FIG.
6
). As a result, power consumption imbalance causes signal skew and noise imbalance.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a semiconductor memory device, which can uniformly maintain power consumption in selecting sub-wordline activation signals, respectively.
According to an aspect of the present invention, a semiconductor memory device comprises a plurality of sub-array blocks. Each of the sub-array blocks includes a plurality of sub-arrays; a plurality of main wordlines arranged through the sub-arrays; a plurality of sub-wordlines arranged in each of the sub-arrays, corresponding to each of the main wordlines; and driving means having a plurality of sub-wordline drive units. Each of the sub-wordline drive units drives one of the sub-wordlines in each of the sub-arrays corresponding to a selected main wordline in response to sub-wordline activation signals. The sub-wordline activation signals are irregularly arranged in the sub-wordline drive units of each of the sub-array blocks such that power consumption is not imbalanced when each of the sub-wordline activation signals is enabled.
Each of the sub-wordline activation signals has boosting voltage level higher than power supply voltage level when they are enabled. The plural sub-wordline drive units include first, second, and third sub-wordline drive units. The plural sub-arrays in each of the sub-array blocks includes a first sub-array arranged between the first and second sub-wordline drive units, an

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