Semiconductor memory device having hierarchical word line struct

Details Semiconductor memory device having hierarchical word line struct Semiconductor memory device having hierarchical word line struct

1999-01-13

2000-12-05

Mai, Son

Static information storage and retrieval

Read/write circuit

Differential sensing

365206, 365 51, 365 63, G11C 702

Patent

active

061575887

ABSTRACT:
First and second global input/output lines are twisted between first and second main blocks. First and second SD signal lines in the first main block are respectively arranged adjacent to first and second global input/output lines. First and second SD signal lines in the second main block are respectively arranged adjacent to the second and first global input/output lines. An SD signal supplied for the first or second SD signal line makes noises applied to the first and second global input/output lines identical, so that an influence by the noises is substantially eliminated between the first and second global input/output lines. As a result, the global input/output line is provided with higher resistance to noise without any increase in a layout area.

REFERENCES:
patent: 5715189 (1998-02-01), Asakura
patent: 5793664 (1998-08-01), Nagata et al.
patent: 5875149 (1999-02-01), Oh et al.

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