Semiconductor memory device having hierarchical bit line structu

Details Semiconductor memory device having hierarchical bit line structu Semiconductor memory device having hierarchical bit line structu

1994-10-12

1996-02-27

Nelms, David C.

Static information storage and retrieval

Systems using particular element

Capacitors

365 52, 365 63, 365190, 36523003, G11C 1124

Patent

active

054954401

ABSTRACT:
A memory cell array is divided into a plurality of memory cell groups in the column direction. In each memory cell group, a sub-bit line SBL and a sub-cell plate line SCPL are located. A pair of main bit lines are arranged for memory cells on one column. For each sub-cell plate line, a switching transistor is provided connecting the sub-cell plate line to one main bit line in response to a group select signal. For each sub-bit line, a switching transistor is provided connecting corresponding sub-bit lines to the other main bit line in response to a group select signal BS. A constant voltage VBL is transmitted to the sub-cell plate line through a switching transistor rendered conductive in response to a group select signal CPPR. A dynamic type semiconductor memory device is provided whose memory array layout is facilitated and in which a sufficient read potential difference is produced on a pair of bit lines upon word line selection.

REFERENCES:
patent: 4926382 (1990-05-01), Sakui et al.
patent: 5353255 (1994-10-01), Komuro
patent: 5367481 (1994-11-01), Takase et al.
"Cell-Plate Line Connecting Complementary Bit-Line (C.sup.3) Architecture for Battery-Operating DRAMS's", Mikio Asakura et al., IEEE Journal of Solid-State Circuits, vol. 27, No. 4, Apr. 1992, pp. 597-602.

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