Active solid-state devices (e.g. – transistors – solid-state diode – Fet configuration adapted for use as static memory cell
Reexamination Certificate
2000-12-15
2002-06-18
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Fet configuration adapted for use as static memory cell
C257S368000, C257S369000, C365S205000
Reexamination Certificate
active
06407463
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device such as static random access memory (SRAM).
2. Description of the Related Art
SRAM, which is one variety of semiconductor memory device, does not require any refresh operation and thus can be used for implementing simpler systems with lower power consumption. That is why SRAM is suitable for use as memory in portable equipment such as cellular telephones.
There is a demand for portable equipment that is even more compact, and the memory cell size of SRAM must be made smaller to address that demand.
SUMMARY OF THE INVENTION
An objective of the present invention is to provide a semiconductor memory device that makes it possible to reduce the memory cell size.
A semiconductor memory device in accordance with the present invention relates to a semiconductor memory device which stores data by a flip-flop configured of a first inverter and a second inverter, the semiconductor memory device comprising:
a first gate electrode layer and a second gate electrode layer;
a first drain- drain contact layer and a second drain- drain contact layer; and
a first drain-gate contact layer and a second drain-gate contact layer,
wherein each of the first and second inverters comprises a load transistor and a drive transistor,
wherein each of the first and second gate electrode layers comprises gate electrodes of the load transistor and the drive transistor,
wherein each of the first and second drain- drain contact layers connects a drain of the load transistor to a drain of the drive transistor,
wherein the first and second gate electrode layers are positioned between the first drain- drain contact layer and the second drain- drain contact layer,
wherein the first drain-gate contact layer connects the first drain- drain contact layer to the second gate electrode layer,
wherein the second drain-gate contact layer connects the second drain- drain contact layer to the first gate electrode layer, and
wherein the first and second drain-gate contact layers, the first and second drain- drain contact layers, and the first and second gate electrode layers are each formed in different layers.
The semiconductor memory device in accordance with the invention makes it possible to reduce the memory cell size. The reasons therefor are discussed below. A flip-flop is configured by connecting an input terminal (gate electrode) of a first inverter to an output terminal (drain) of a second inverter, and by connecting an input terminal (gate electrode) of the second inverter to an output terminal (drain) of the first inverter. In other words, the flip-flop is configured by cross-coupling the first inverter and the second inverter.
When the flip-flop is fabricated in two layers, the cross-coupling connection could be enabled by having the drain- drain contact layer for connecting together the drains of the inverters and the drain-gate contact layer for connecting the gate of one inverter to the drain of the other inverter in the same layer, by way of example.
However, such a configuration would mean that this conductive layer would be formed to extend over a region in which the drain of the first inverter is positioned, a region in which the gate of the second inverter is positioned, and a connecting region therebetween. Thus, this conductive layer would require a pattern having three end portions (such as a pattern with branch points, such as a T-shaped or small h-shaped pattern) or a spiral pattern with interlocking arm portions. Note that an example of a T-shaped pattern is disclosed in
FIG. 1
of Japanese Patent Application Laid-Open No. 10-41409. An example of a small h-shaped pattern is disclosed in FIG.
4
(
b
) on page 203 of “the IEDM Tech. Digest (1998)”, by M. Ishida, et al. An example of a spiral pattern is disclosed in FIG.
3
(
b
) on page 203 of “the IEDM Tech. Digest (1998)”, by M. Ishida, et al.
If such a complicated pattern is reduced in size, it would be difficult to reproduce that shape accurately in a photoetching step, so that the desired pattern will not be obtained and thus it will not be possible to reduce the memory cell size.
In a semiconductor memory device in accordance with the present invention, a gate electrode layer that forms gates for the inverters, a drain- drain contact layer that connects together the drains of the inverters, and a drain-gate contact layer that connects the gate of the first inverter to the drain of the second inverter are formed in different layers. In this manner, the semiconductor memory device in accordance with the present invention uses three layers in the fabrication of the flip-flop. This makes it possible to simplify the pattern of each layer (by making them linear, by way of example), in comparison with a flip-flop formed by using two layers.
In the above described manner, a semiconductor memory device in accordance with this aspect of the present invention makes it possible to simplify the pattern of each layer and thus create a semiconductor memory device having a memory cell size with dimensions of 4.5 &mgr;m
2
or less.
In the semiconductor memory device in accordance with the present invention, first and second gate electrode layers are positioned between the first drain- drain contact layer and the second drain-drain contact layer. This makes it possible to dispose the source contact of each drive transistor in the center of the memory cell. This increases the degree of freedom in the fabrication of the first and second drain-gate contact layers, which further helps in reducing the memory cell size.
It is possible to apply this aspect of the present invention with the above-described configuration to a semiconductor memory device having a memory cell that comprises a plurality of transfer transistors and a flip-flop configured of first and second inverters.
In the semiconductor memory device in accordance with the present invention,
the first gate electrode layer, the second gate electrode layer, the first drain- drain contact layer, and the second drain- drain contact layer may be disposed to be mutually parallel and each may form a linear pattern.
This configuration makes it possible to simplify the patterning, thus enabling a semiconductor memory device with a smaller memory cell size.
The semiconductor memory device in accordance with the present invention may further comprise:
a first contact conductive portion and a second contact conductive portion, and
the first contact conductive portion may be formed in a hole and is connected to the second gate electrode layer,
the second contact conductive portion may be formed in a hole and is connected to the first gate electrode layer,
the first drain-gate contact layer may be connected to the first contact conductive portion,
the second drain-gate contact layer may be connected to the second contact conductive portion,
the first and second contact conductive portions may be positioned between the first drain-gate contact layer and the second drain-gate contact layer,
the first contact conductive portion may be positioned closer to the first drain-gate contact layer than the second contact conductive portion, and
the second contact conductive portion may be positioned closer to the second drain-gate contact layer than the first contact conductive portion.
In this configuration, the first contact conductive portion is positioned closer to the first drain-gate contact layer than the second contact conductive portion and the second contact conductive portion is positioned closer to the second drain-gate contact layer than the first contact conductive portion. Thus the distance between the first drain-gate contact layer and the second drain-gate contact layer can be reduced in this configuration making it possible to reduce the size of the memory cell. This will be described in more detail in the section on an embodiment of the present invention.
In the semiconductor memory device in accordance with the present invention,
each of the first and second drain-gate contact layers may have a p
Kodaira Satoru
Kumagai Takashi
Noda Takafumi
Takeuchi Masahiro
Ho Tu-Tu
Nelms David
Oliff & Berridg,e PLC
Seiko Epson Corporation
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