Semiconductor memory device having floating body cell

Details Semiconductor memory device having floating body cell Semiconductor memory device having floating body cell

2007-12-04

2009-10-13

Luu, Pho M. (Department: 2824)

Static information storage and retrieval

Read/write circuit

For complementary information

C365S205000, C365S206000, C365S207000

Reexamination Certificate

active

07602657

ABSTRACT:
A semiconductor memory device includes a sense amplifier for the FBC, a first node and a second node can be disconnected from each other by a first isolation transistor. A third node and a fourth node can be disconnected from each other by a second isolation transistor. The first node is connected to the first memory cell. The third node is connected to the second memory cell. A first amplification transistor and a second amplification transistor are connected between the first node and the third node. A third amplification transistor and a fourth amplification transistor are connected between the second node and the fourth node. This enables to parallelly execute read data transfer to the data lines and precharge to prepare for the next read operation.

REFERENCES:
patent: 7313041 (2007-12-01), Chapman et al.
patent: 7376031 (2008-05-01), Ohsawa
Takashi Ohsawa, et al., “Design of a 128-Mb SOI DRAM Using the Floating Body Cell (FBC)”, IEEE Journal of Solid-State Circuits, vol. 41, No. 1, Jan. 2006, pp. 135-145.
Takashi Ohsawa, et al., “An 18.5ns 128Mb SOI DRAM with a Floating Body Cell”, IEEE International Solid-State Circuits Conference (ISSCC 2005), Session 25, Dynamic Memory, 25.1, Feb. 9, 2005, pp. 458-459 and 609.

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