Static information storage and retrieval – Magnetic bubbles – Velocity
Reexamination Certificate
2001-03-27
2002-05-21
Phan, Trong (Department: 2818)
Static information storage and retrieval
Magnetic bubbles
Velocity
C365S225700, C365S233100
Reexamination Certificate
active
06392909
ABSTRACT:
BACKGROUND
1. Technical Field
The present invention relates generally to a semiconductor memory device and, more particularly, to a system and method for providing various CAS latencies during testing of a synchronous dynamic random access memory (SDRAM) while providing a fixed CAS latency during operation of the SDRAM.
2. Description of Related Art
In general, the term CAS latency refers to the amount of time (typically measured in clock cycles) between a request to read memory and when the data is actually output. In particular, with SDRAMs, after a predetermined number of clock cycles have lapsed from an external command, e.g., a read command, that is received in synchronization with an external clock signal, data is output from a SDRAM memory cell corresponding to the command in synchronization with a clock signal. CAS latency refers to the number of required clock cycles that occur from the initial clock signal that is synchronized with the external command to the clock signal that is synchronized with the data output operation.
Conventionally, as illustrated in
FIG. 1
, the CAS latency for a SDRAM may be set by information bits that are stored in a mode register set (hereinafter referred to as “MRS”) within the SDRAM. For example, when a MRS command of a SDRAM is input, predetermined address signals (such as values applied to addresses A
4
, A
5
, and A
6
) are stored in the MRS to thereby set the CAS latency. Thus, the CAS latency can be arbitrarily set for any desired time period such that a SDRAM outputs data after a predetermined number of clock cycles (corresponding to the set CAS latency) have occurred from the occurrence of a clock signal synchronized with an external (e.g., read) command.
Furthermore, in a system in which the SDRAM is used for a specific purpose and a fixed CAS latency is required, the CAS latency may be set as a fixed value. Even for implementations in which a fixed latency is required, it would be highly desirable to design the SDRAM such that various CAS latencies may be implemented to test whether the SDRAM will operate using such various CAS latencies after the fabrication process. Thus, there is a need for a semiconductor memory device having an architecture that provides a fixed CAS latency during a normal mode of operation and various CAS latencies during a test mode of operation.
SUMMARY OF THE INVENTION
The present invention is directed to a semiconductor memory device that provides a fixed column address strobe (CAS) latency during a normal operation mode as well as various CAS latencies in a test mode. In one aspect of the present invention, a semiconductor memory device comprises:
a master signal generator for generating a master signal in response to one of a power-up signal, a latency test signal and a combination thereof;
a plurality of fuse information units for generating fuse information signals in response to one of the power-up signal, the master signal and a combination thereof;
a plurality of mode register set (MRS) address information units which receive address bits during an interval where an address window signal is activated to generate MRS address latch signals in response to a MRS addressing signal; and
a CAS latency determining unit for generating CAS latency select signals in response to the fuse information signals and the MRS address latch signals, wherein the CAS latency select signals provide one of a fixed CAS latency during first mode of operation of the semiconductor device and varying CAS latencies during a second mode of operation of the semiconductor device.
In another aspect of the present invention, a semiconductor memory device comprises:
a first circuit for generating a first control signal and a complementary first control signal in response to a power-up signal and a latency test signal;
a second circuit, responsive to the complementary first control signal, for generating a plurality of second control signals;
a third circuit, responsive to an address signal, for generating a plurality of third control signals; and
a fourth circuit, responsive to the first control signal, for selectively processing the second control signals and third control signals to provide one of a fixed CAS latency during a first mode of operation of the semiconductor device and a plurality of CAS latencies during a second mode of operation of the semiconductor device.
In yet another aspect of the invention, a method for providing a CAS latency in a semiconductor memory device comprises the steps of:
generating a first control signal indicative of a fixed CAS latency;
generating a second control signal indicative of one of a plurality of non-fixed CAS latencies; and
selectively processing one of the first and second control signals during one of a first mode of operation of the semiconductor device to provide the fixed CAS latency and a second mode of operation of the semiconductor device to provide one of the non-fixed CAS latencies.
These and other aspects, features, and advantages of the present invention will become apparent from the following detailed description of the preferred embodiments, which is to be read in connection with the accompanying drawings.
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patent: 6081476 (2000-06-01), Hotta
patent: 6084803 (2000-07-01), Sredanovic et al.
patent: 6104668 (2000-08-01), Lee et al.
patent: 6215725 (2001-04-01), Komatsu
patent: 6084350 (1994-03-01), None
Abstract for JP6084350.
Jang Tae-seong
Yoo Tae-jin
F. Chau & Associates LLP
Phan Trong
Samsung Electronics Co,. Ltd.
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