Semiconductor memory device having error checking and correcting

Details Semiconductor memory device having error checking and correcting Semiconductor memory device having error checking and correcting

1990-08-21

1992-12-15

Popek, Joseph A.

Static information storage and retrieval

Read/write circuit

Testing

365200, 365 63, 371 213, 371 401, G06F 1110, G11C 2900

Patent

active

051723395

ABSTRACT:
A semiconductor memory device having an error checking and correcting (ECC) circuit is disclosed. This memory device includes data lines (10-21) from an ECC data generation circuit and bit lines (30-41) connected to the adjacent memory cells in a memory array (1), which are selectively connected at specified connecting portions (51, 52). When predetermined test data is inputted in order to detect undesired contact or interference between the memory cells, checker pattern data can be written in all the memory cells. Thus, despite the fact that the memory device includes an ECC circuit, a complete and easy memory cell checking is carried out.

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patent: 4811294 (1989-03-01), Kobayashi et al.
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Davis, "A 70-ns Word-Wide 1-Mbit ROM With On-Chip Error-Correction Circuits", IEEE Journal of Solid-State Circuits, vol. SC-20, No. 5, Oct. 1985, pp. 958-963.
Holscher et al., "Mikrocomputer in der Sicherheitstechnik", Sep., 1984.

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