Semiconductor memory device having dummy cells around memory...

Details Semiconductor memory device having dummy cells around memory... Semiconductor memory device having dummy cells around memory...

1999-12-17

2002-08-20

Elms, Richard (Department: 2824)

Static information storage and retrieval

Read/write circuit

Differential sensing

C365S145000, C365S200000

Reexamination Certificate

active

06438052

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to a semiconductor memory device and, more particularly, to a semiconductor memory device of the type storing binary data bits in the form of voltage level such as, for example, a dynamic random access memory device and a ferroelectric random access memory device and a power supply system incorporated therein.
DESCRIPTION OF THE RELATED ART
Various kinds of semiconductor memory devices are known. A semiconductor random access memory device and a semiconductor read only memory device are typical examples, and a wide variety of application has been found. A dynamic random access memory cell and a ferroelectric random access memory cell store binary data bits in the form of potential level. Semiconductor device manufacturers have been requested to increase the data storage capacity of the dynamic random access memory device and the ferroelectric random access memory device without enlargement of the semiconductor chips. The semiconductor device manufacturers integrate circuit components at a high density. The higher the integration density, the lower the production yield. There are various origins of the defective products. One of the origins is a discontinuity of the circuit pattern to be transferred to a photo-sensitive layer spread over the semiconductor wafer. In detail, a defect is less likely to take place in the portion where the circuit pattern is two-dimensionally repeated. However, the circuit pattern is discontinued in the peripheral area of the portion assigned to the memory cell array. The defect is more likely to take place in the peripheral area.
In order to compromise the high integration density and the high production yield, a solution is proposed in Japanese Patent Publication of Unexamined Application No. 61-214559. The solution is to arrange dummy cells around the memory cell array. The dummy cell is not used for storing a data bit, but is formed from the circuit patterns same as those for the memory cells.
FIG. 1
shows a typical example of the semiconductor dynamic random access memory device of the type having the dummy cells. The prior art semiconductor dynamic random access memory device
100
has memory cell arrays
101
arranged in rows and columns, and each of the memory cell arrays
101
is assigned a square area. The square areas are also arranged in rows and columns.
The memory cell arrays
101
are associated with sub-word line driver units
102
, and the sub-word line driver units
102
are alternated with the square areas in the direction of row. The memory cell arrays
101
are further associated with sense amplifier units
103
, and the sense amplifier units
103
are alternated with the square areas in the direction of column. The sub-word line driver units
102
and the sense amplifier units
103
are abbreviated as “SWD” and “SAMP”, respectively.
The rows of memory cell arrays
101
are associated with row address decoder units
104
, respectively, and the row address decoder units
104
are operative to selectively make the sub-word line decoder units
102
responsive to row address predecoded signals. The row address decoder units
104
are located on the right sides of the rows of memory cell arrays
101
. On the other hand, the columns of memory cell arrays
101
are associated with column address decoder/selector units
105
, respectively, and the column address decoder/selector units
105
are located on the lower ends of the columns of memory cell arrays
101
. The row address decoder units
104
and the column address selector/decoder units
105
are abbreviated as “XDEC” and “YDEC”, respectively.
The row address decoder units
104
and the column address selector/decoder units
105
are connected to peripheral circuits
106
, and a power source
107
and input/output circuits (not shown) are examples of the peripheral circuits
106
.
FIG. 2
shows one of the memory cell arrays
101
, and
FIGS. 3
,
4
and
5
show different cross sections of the structure of the memory cell array
101
. Although first capacitor electrodes
115
, a second capacitor electrode
116
, sub-word lines
117
, bit lines
118
and impurity regions
119
are formed on different levels of the structure (see
FIGS. 3
to
5
), they are drawn by using real lines, and broken lines are used only for some memory cells
112
and some dummy cells
113
so as to make the memory cells
112
and the dummy cells
113
discriminative from them. The first capacitor electrodes
115
are indicated by hatching lines for the sake of clear discrimination, and mark “x” is indicative of the location of each via-hole formed in inter-level insulating layers. However, the inter-level insulating layers are deleted from the layout shown in FIG.
2
.
The square area assigned to each memory cell array
101
is broken down into a central sub-area
110
assigned to the memory cells
112
and peripheral sub-areas
111
assigned to the dummy cells
113
. Each of the memory cells
112
are implemented by the combination of a transfer transistor
114
and a storage capacitor, and the first capacitor electrode
115
, a dielectric layer (not shown) and a part of the second capacitor electrode
116
form in combination each storage capacitor. The transfer transistor
114
and the storage capacitor constitute each of the dummy cells
113
. Thus, the memory cells
112
are identical with the dummy cells
113
as will be described hereinbelow. The impurity regions
119
are arranged in a staggered manner over the square area, and are identical in configuration with one another. Pairs of memory cells
112
are respectively assigned to the impurity regions
119
in the central sub-area
110
, and pairs of dummy cells
113
are respectively assigned to the impurity regions
119
in the peripheral sub-areas
111
. The sub-word lines
117
extend over the impurity regions
119
in the direction of row, and serve as gate electrodes of the transfer transistors
114
. The sub-word lines
117
are connected to the associated sub-word driver units
102
. The bit lines
118
extend over the sub-word lines
117
and, accordingly, the impurity regions
119
in the direction of column, and are connected through the via-holes to the associated impurity regions
119
(see FIGS.
3
and
5
). The bit lines
118
serve as source electrodes of the transfer transistors
114
. The sub-word line
117
is shared between the memory cells
112
and the dummy cells
113
forming parts of the same row. The bit lines
118
for the memory cells
112
are connected to the associated sense amplifier unit
103
. However, the bit lines
118
for the dummy cells
113
are connected to a source of ground level.
The impurity region
119
is further connected at both end portions thereof to the first capacitor electrodes
115
through the via-holes. Both end portions of the impurity region
119
serve as drain regions of the transfer transistors
114
of the associated pair. The first capacitor electrodes
115
are higher than the bit lines
118
(see FIG.
4
), and are covered with the dielectric layers (not shown). The second capacitor electrode
116
is held in contact with the dielectric layers of the storage capacitors, and is shared between the memory cells
112
and the dummy cells
113
of the memory cell array
101
.
The second capacitor electrode
116
is applied with a potential level half as high as the internal power voltage generated by the power source
107
. The sub-word line decoder units
102
, the sense amplifier units
103
, the column address decoder/selector units
105
and the peripheral circuits
106
are powered by the power source
107
.
Row addresses are respectively assigned to the sub-word lines
117
, and column addresses are respectively assigned to the bit lines
118
associated with the columns of memory cells
112
. Thus, each memory cell
112
is selected from the memory cell array
101
by using the combination of the row address and the column address.
When the row address and the column address specify a memory cell
112
, the peripheral circuits
1

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