Semiconductor memory device having disturb test circuit

Details Semiconductor memory device having disturb test circuit Semiconductor memory device having disturb test circuit

2001-10-15

2003-04-22

Nelms, David (Department: 2818)

Static information storage and retrieval

Read/write circuit

Bad bit

C365S201000, C365S185090

Reexamination Certificate

active

06552939

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to a semiconductor memory device, and in particular to a disturb test system using a flexible redundancy technique for a high-density semiconductor memory device and the like semiconductor integrated circuit having a redundant construction.
2. Description of the Prior Art
In a conventional semiconductor memory device, in order to improve a yield or recovery, when there exists a defect in the memory device, the defective element is repaired by replacement with a correct element of a redundant circuit, using such as a laser trimming method. Therefore, the memory device per se must be previously provided with a redundant circuit block.
FIG. 8
shows an example of a conventional memory cell array construction of a redundant distribution type. In the construction of this type, the memory cell array is comprised of a plurality of memory sub array blocks (SAB
0
to SAB
3
). The sub array blocks include corresponding normal blocks (NBL
0
to NBL
3
) and corresponding redundant blocks (RBL
0
to RBL
3
) which are controlled upon receipt of address selection signals from corresponding program circuits (PRO
0
to PRO
3
). Each of the normal blocks is formed of normal memory cells and each of the redundant blocks is formed of redundant cells.
In recent years, in order to improve a yield with reduction in chip area, there is developed a flexible redundancy construction of a shared redundancy type as shown in FIG.
9
. In this construction, a plurality of redundant blocks are concentrated as one redundant block RBL located in one particular memory sub array block (e.g., SAB
2
in
FIG. 9
) and replacement of a defect element in a normal block in one memory sub array is executed using a redundant element provided in the redundant block.
When a redundant element is to be used, a corresponding spare word line enable signal SWLE is activated and a corresponding normal word line enable signal NWLE is inactivated. On the contrary, when a redundant element is not to be used, a spare word line enable signal SWLE is inactivated and a corresponding normal word line enable signal NWLE is activated.
In a usual redundant replacement, selection of using a redundant element in place of a normal defective element is executed by a known technique of blowing a fuse in a laser trimmer for electrically melting a non-use fuse and connecting another fuse to be used in a program circuit, thereby controlling the selection of a redundant circuit in accordance with an address to be replaced.
Thus, in the conventional semiconductor memory device, repair efficiency is enhanced and the occurrence of a defective product is prevented by replacement of a defect element with a redundant element over different sub arrays SAB
0
to SAB
3
as shown in FIG.
9
.
On the other hand, a disturb refresh test for a semiconductor memory device is carried out for examining a storage state of the memory cell. In the disturb refresh test, a reading operation of a word line of interest is repeated, that is, the word line of interest is repeatedly turned on/off for a predetermined period to create a situation where a leakage is easily caused in a memory cell in the vicinity of the word line of interest. In this manner, the storage state of the memory cell is tested.
However, in a flexible type redundant configuration as shown in
FIG. 9
, a defective element included in one normal sub array block may be replaced with a redundant element included in another sub array block in many cases. Therefore, there is a problem that a defective portion can not be detected or detection ability of a defective portion is undesirably lowered because of the following reasons as to be described below.
FIG. 10
shows an example of a general memory cell array construction of a dynamic random access memory (referred to “DRAM” hereinafter). In this construction, a plurality of sense amplifiers (S/A
0
, . . . , S/A
3
) are connected to corresponding bit line pairs (Bit #
0
, /Bit #
0
, . . . , Bit #
3
, /Bit #
3
), respectively, and each of the bit lines has a plurality of activation regions through bit line contacts BLC. The memory cell array further includes a plurality of word lines (WL
0
to WL
8
) so that interest storage nodes SN of the memory cells are designated by the bit lines and the word lines.
The following describes a case where there is a leakage or short-circuit due to such as an electrically conductive foreign or extraneous substance or dusts between a storage node of a cell A and a storage node of an adjacent cell B.
In the case where an address of the adjacent cell B sharing a bit line contact hole BLC
3
with the cell A is replaced by an address of a redundant circuit, namely, in the case where, for example, a word line WL
3
having a defect is replaced by a redundant circuit, the word line WL
3
of an adjacent address can not be activated after the replacement is executed. Therefore, reverse data with respect to data stored in the cell A can not be stored in the adjacent bit cell B which is short-circuited to the cell A by the leakage.
As a result, even when there exists a leakage between the cell A and the adjacent cell B, the defective portion can not be fully detected in a disturb refresh test once the replacement was executed.
This is because, in a usual replacement, the selection of a redundant sub array block in place of a normal sub array block is executed by blowing a fuse, using a laser trimming technique for electrically melting a fuse in the program circuit. Thus, the program circuit controls the redundant circuit in accordance with an address of a defective element to be replaced. However, once such replacement with a redundant circuit is carried out, the fuse connection state in the program circuit can not be immediately restored to the previous or original state. Accordingly, the word line of interest for selecting the defective cell B can not be activated after the replacement was carried out. Therefore, the adjacent cell B short-circuited to the cell A can not be written with the reverse data with respect to the data written in the cell A.
Referring to
FIG. 11
, the following describes a case where there is a short-circuit between a storage node of the cell A and an adjacent bit line (e.g., Bit
2
in
FIG. 11
) due to such as a conductive foreign substance or dusts.
In order to detect this defect, data of high level “H” has been previously written in the cell A and then the level of the adjacent bit line Bit
2
is made low “L” in the disturb refresh test. In this case, since the level of the bit line must be changed under the condition that the cell A is kept in the non-selected state, the level of the bit line is changed by a sense operation in the manner same as that when accessing the cell data within the same sub array block.
Therefore, in the case of the redundancy distribution type where the redundant circuit used for replacement is located in the same sub array block of the normal block as shown in
FIG. 8
, the bit line level of interest can be determined. However, in the case of the flexible type redundancy construction as shown in
FIG. 9
, when the word line is replaced by a redundant circuit located in a sub array block other than that of the word line WL
4
selecting the cell A, the redundant block RBL is kept in the non-selected condition unless the word line WL
4
is selected. Therefore, this block is set to be a stand-by state. That is, in the stand-by condition, the level is generally equalized to ½ VDDS level which corresponds to a power supply level for a sense amplifier (S/A#
0
to S/A#
3
). Therefore, the disturb refresh test can not be fully executed for detecting a defective portion.
Also, in the case where a part of other than the word line WL
4
is replaced by a redundant circuit of a different sub array block, the frequency of accessing the bit line is lowered, and therefore the disturb refresh test can not be fully executed. Therefore, there is a problem that it takes mor

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