Semiconductor memory device having data masking pin and...

Details Semiconductor memory device having data masking pin and... Semiconductor memory device having data masking pin and...

2001-06-21

2002-10-01

Le, Vu A. (Department: 2824)

Static information storage and retrieval

Addressing

Sync/clocking

C365S193000, C711S105000

Reexamination Certificate

active

06459651

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device and a memory system including the same, and more particularly, to a synchronous DRAM which can mix memory modules having different structures in a memory system and a memory system including the same.
2. Description of the Related Art
In order to increase system performance, the integration density and speed of semiconductor memory devices such as DRAM, must be increased. That is, DRAM which can process more data at faster speed is required. Accordingly, a synchronous DRAM which operates in synchronization with a system clock signal for high speed operation was developed, and the appearance of the synchronous DRAM remarkably enhanced data transmission speed.
However, in the synchronous DRAM, input and output of data must be performed within one cycle of the system clock signal, so that there is a limit to an increase in bandwidth between the synchronous DRAM and a DRAM controller, that is, there is a limit to an increase in the amount of data that can be input to and output from a memory device per unit time. Therefore, in order to further increase data transmission speed, a dual data rate (DDR) synchronous DRAM in which a rising edge and a falling edge of a data strobe signal are all synchronized to input and output data was developed.
FIG. 1
is a schematic block diagram illustrating a memory system including a DDR synchronous DRAM. Referring to
FIG. 1
, in a memory system including a DDR synchronous DRAM, a system clock signal (CK) generated by a clock driver
17
is transmitted to DDR synchronous DRAMs
15
on memory modules
13
. An address (ADD) and a command (COM) are transmitted from a memory controller
11
to the DDR synchronous DRAMs
15
on the memory modules
13
during writing and reading operations.
Data (DQ) and a data strobe signal (DQS) are transmitted from the memory controller
11
to the DDR synchronous DRAMs
15
on the memory modules
13
during writing. The DQ and DQS signals are transmitted from the DDR synchronous DRAMs
15
on the memory modules
13
to the memory controller
11
during reading. That is, the data (DQ) and the data strobe signal (DQS) are transmitted in both directions. A data masking signal (DM) is generated in and output from the memory controller
11
during writing and transmitted to the DDR synchronous DRAMS
15
on the memory modules
13
.
The data strobe signal (DQS) is a signal for strobing input and output of the data (DQ), and the data masking signal (DM) is a signal for masking predetermined data input into the DDR synchronous DRAMs
15
during writing. In general, one data strobe signal (DQS) and one data masking signal (DM) are assigned per 4 bits of data in the synchronous DRAM having x4 organization and assigned per 8 bits of data in the synchronous DRAM having x8 organization.
Therefore, as shown in
FIG. 2
, if a module (x4 module) including synchronous DRAMs having x4 organization is not mixed with a module (x8 module) including the synchronous DRAMs having x8 organization in the memory system shown in
FIG. 1
, a relationship between the data (DQ) and the data strobe signal (DQS) is always regular. That is, when memory modules (
13
-
1
through
134
) are all x4 modules, the data (DQ) is N bits, and the number of the data strobe signals (DQS) is N/4. If the memory modules (
13
-
1
through
13
-
4
) are all x8 modules, the data (DQ) is N, and the number of the data strobe signals (DQS) is N/8.
When data is read from each of the memory modules (
13
-
1
through
13
-
4
), the number of data strobe signals (DQS) transmitted from each of the memory modules (
13
-
1
through
13
-
4
) to the memory controller
11
is the same. The number of data strobe signals (DQS) that the memory controller
11
uses for receiving data read from each of the memory modules (
13
-
1
through
13
-
4
) is the same. Therefore, the memory controller
11
can easily receive data read from each of the memory modules (
13
-
1
through
13
-
4
) using the same number of data strobe signals (DQS).
However, as shown in
FIG. 3
, if the x4 module is mixed with the x8 module in the memory system shown in
FIG. 1
, a relationship between the data (DQ) and the data strobe signal (DQS) is irregular. Here, it is assumed that memory modules (
13
-
5
and
13
-
8
) are the x4 modules and memory modules (
13
-
6
and
137
) are the x8 modules.
In this case, when data is read from each of the memory modules (
13
-
5
through
13
-
8
), the number of data strobe signals (DQS) transmitted from the x4 modules, that is, the memory modules (
13
-
5
and
13
-
8
) to the memory controller
11
is different from the number of data strobe signals (DQS) transmitted from the x8 modules, that is, the memory modules (
13
-
6
and
13
-
7
), to the memory controller
11
. The number of data strobe signals (DQS) which the memory controller
11
uses for receiving data read from the x4 modules (
13
-
5
and
13
-
8
) is different from the number of the data strobe signals (DQS) that the memory controller
11
uses for receiving data read from the x8 modules (
13
-
6
and
13
-
7
).
For example, when N bits of the data (DQ) are read from the x4 modules (
13
-
5
and
13
-
8
), N/4 (set
0
and set
1
) of data strobe signals (DQS) are transmitted from the x4 modules (
13
-
5
and
13
-
8
) to the memory controller
11
, but when N bits of the data (DQ) are read from the x8 modules (
13
-
6
and
13
-
7
), N/8 (set
0
) of the data strobe signals (DQS) are transmitted from the x8 modules (
13
-
6
and
13
-
7
) to the memory controller
11
.
Therefore, when the x4 modules are mixed with the x8 modules in a memory system, it is difficult for the memory controller to determine which data strobe signals to use for receiving data when reading data from the modules. Therefore, memory modules having the same organization must be included in the memory system.
SUMMARY OF THE INVENTION
To solve the above problems, it is a first objective of the present invention to provide a synchronous DRAM which can mix memory modules having different organizations in a memory system.
It is a second objective of the present invention to provide a memory system in which memory modules having different organizations can be mixed.
In accordance with the invention, there is provided a semiconductor memory device, for example, a synchronous DRAM, which operates in synchronization with a system clock signal and inputs and outputs data in response to a data strobe signal. The device includes a data masking pin which receives a data masking signal for masking input data during a memory writing operation. In accordance with the invention, the same signal as the data strobe signal is output through the data masking pin during a memory reading operation.
The device of the invention can operate in synchronization with the rising edge and falling edge of the system clock signal.
In one embodiment, the synchronous DRAM further includes a data masking signal input buffer for buffering the data masking signal received through the data masking pin and outputting it to an internal circuit, and an auxiliary data strobe signal output buffer for buffering an internal data strobe signal generated internally and outputting it to the data masking pin.
The synchronous DRAM can further include a mode register which can be controlled externally, wherein the auxiliary data strobe signal output buffer is controlled by the mode register.
In accordance with another aspect, there is provided in accordance with the invention a memory system comprising at least one first memory module which operates in synchronization with a system clock signal, and inputs and outputs data in response to each of one or more data strobe signals. The system also includes at least one second memory module which operates in synchronization with the system clock signal, and inputs and outputs data in response to each of the data strobe signals. A memory controller controls the first and second memory modules, and transmits and receives

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