Semiconductor memory device having data holding mode using...

Details Semiconductor memory device having data holding mode using... Semiconductor memory device having data holding mode using...

2006-05-19

2010-10-19

Chaudry, M. Mujtaba K (Department: 2112)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

C714S763000

Reexamination Certificate

active

07818651

ABSTRACT:
When memory cells enter a data holding mode, a control circuit of a semiconductor memory device reads out a plurality of data from the memory cells to generate and store a check bit for error detection and correction, and performs a refresh operation in a period within an error occurrence allowable range of an error correcting operation performed by an ECC circuit by using the check bit. Before a normal operation mode is restored from the data holding mode, the control circuit performs control such that an error bit of the data is corrected by using the check bit. In an entry/exit period, read and write are performed by a page operation.

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