Semiconductor memory device having data erasing mechanism

Details Semiconductor memory device having data erasing mechanism Semiconductor memory device having data erasing mechanism

1997-01-21

1998-05-12

Le, Vu A.

Static information storage and retrieval

Read/write circuit

Using different memory types

36518924, 36518928, G11C 700

Patent

active

057516367

ABSTRACT:
In this invention, charges are extracted from the charge storage portion by means of F-N tunnel current, and then avalanche hot carriers are injected into the storage portion.

REFERENCES:
patent: 4173791 (1979-11-01), Bell
patent: 4503519 (1985-03-01), Arakawa
patent: 4742491 (1988-05-01), Liang et al.
patent: 4884239 (1989-11-01), Ono et al.
patent: 5272669 (1993-12-01), Samachisa et al.
patent: 5280446 (1994-01-01), Ma et al.
patent: 5289401 (1994-02-01), Shima et al.
patent: 5379256 (1995-01-01), Tanaka et al.
E. Takeda et al., "Device Performance Degradation Due to Hot-Carrier Injection at Energies Below the Si-SiO.sub.2 Energy Barrier", 1983 International Electron Devices Meeting, Article No. 15.5, pp. 396-399, Dec. 1983.
S. Yamada et al., "A Self-Convergence Erasing Scheme for a Simple Stacked Gate Flash EEPROM", 1991 International Electron Devices Meeting, Article No. 11.4, pp. 307-310, Dec. 1991.
K. Naruke et al., "Restraint of Variation in Threshold Voltage to 1/3, Prevention of Excessive Erasion is Flash Type EEPROM", Nikkei Microdevices, pp. 85-91, Feb. 1992.

Affiliated with

Also associated with

Rating

Semiconductor memory device having data erasing mechanism does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor memory device having data erasing mechanism, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor memory device having data erasing mechanism will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-989490