Semiconductor memory device having control circuit

Details Semiconductor memory device having control circuit Semiconductor memory device having control circuit

2006-09-19

2006-09-19

Tran, Denise (Department: 2185)

Electrical computers and digital processing systems: memory

Storage accessing and control

Specific memory composition

C365S222000

Reexamination Certificate

active

07111112

ABSTRACT:
In a freeze reset circuit in a semiconductor memory device, when a row act signal is not activated in a predetermined period determined by a trailing edge delay circuit after a chip enable signal is set to the H level during a write or read operation, a freeze reset signal is output from a logic gate after a predetermined period. As a result, the semiconductor memory device terminates the write or read operation. Therefore, the semiconductor memory device can ensure the stability of the write or read operation.

REFERENCES:
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patent: 6625077 (2003-09-01), Chen
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patent: 2003/0112687 (2003-06-01), Tang
patent: 1998-060894 (1998-10-01), None
Kazuhiro Sawada et al., “A 30-μ A Data-Retention Pseudostatic RAM with Virtually Static RAM Mode”, IEEE Journal of Solid-State Circuits, vol. 23, No. 1, Feb. 1998, pp. 12-19.
Related U.S. Appl. No. 09/987,895, filed Nov. 16, 2001, (Our Ref. No. 57454-291).

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