Semiconductor memory device having consistent skew over...

Details Semiconductor memory device having consistent skew over... Semiconductor memory device having consistent skew over...

2005-06-07

2005-06-07

Nelms, David (Department: 2818)

Static information storage and retrieval

Interconnection arrangements

C365S189050, C365S191000, C710S100000, C710S305000

Reexamination Certificate

active

06903955

ABSTRACT:
A semiconductor memory device including a memory core, a data input circuit, a data output circuit, at least one data input/output line, at least one row control signal and at least one column control signal, wherein the data input circuit and the data output circuit are separately arranged, the memory core is positioned between the data input circuit and the data output circuit, the data input/output line extends from the data input circuit to the data output circuit across the memory core, and the row control signal line and the column control signal line simultaneously start from a first side of the data input circuit, proceed in along a side of the memory core to a corner of the memory core, the core being adjacent to the data output circuit, and then run from the corner to the opposite corner of the memory core.

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