Semiconductor memory device having concurrently resettable memor

Details Semiconductor memory device having concurrently resettable memor Semiconductor memory device having concurrently resettable memor

1990-11-26

1994-02-08

LaRoche, Eugene R.

Static information storage and retrieval

Read/write circuit

Erase

36518904, 365900, G11C 700, G11C 500

Patent

active

052854205

ABSTRACT:
A semiconductor memory device comprises a plurality of memory cells having respective memory circuits for storing data bits each being of either logic "1" or logic "0" level in a rewritable manner, a read-out unit operative to selectively read out the data bits from the memory cells, a write-in unit operative to selectively write data bits into the memory cells, and a resetting unit operative to concurrently write reset data bits of a predetermined logic level into the memory cells, wherein the resetting unit comprises switching transistors respectively coupled to the memory circuits and a source of the predetermined logic level and is responsive to an external reset controlling signal for causing the switching transistors to concurrently turn on, thereby concurrently writing the reset data bits without failure.

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Annex to The European Search Report.

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