Semiconductor memory device having complete hidden refresh...

Details Semiconductor memory device having complete hidden refresh... Semiconductor memory device having complete hidden refresh...

2007-10-24

2008-11-04

Phung, Anh (Department: 2824)

Static information storage and retrieval

Read/write circuit

Data refresh

C365S230060

Reexamination Certificate

active

07447098

ABSTRACT:
In a DRAM having a complete hidden refresh function, when data refresh is to be carried out in an active mode, a signal for selecting a way is set to an “H” level and then reset to an “L” level at each cycle while the corresponding upper address is designated. When data refresh is to be carried out in a standby mode, the signal for selecting the way is maintained at an “H” level and is not reset to an “L” level while the corresponding upper address is designated. This can reduce the standby current.

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