Semiconductor memory device having column redundancy scheme...

Details Semiconductor memory device having column redundancy scheme... Semiconductor memory device having column redundancy scheme...

2001-07-13

2002-07-02

Phan, Trong (Department: 2818)

Static information storage and retrieval

Addressing

Plural blocks or banks

C365S200000

Reexamination Certificate

active

06414896

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor memory devices, and more particularly, to a semiconductor memory device having a column redundancy scheme which improves redundancy efficiency of the semiconductor memory device.
2. Description of the Related Art
A dynamic random access memory (DRAM) is made up of many memory cells. If a semiconductor memory device has even one defective cell of the many memory cells, the semiconductor memory device does not properly operate and is treated as a defective chip. The probability that defective cells occur in a memory device increases due to the recent trend of the high density integration and high speed operation of semiconductor memory devices. As a result, the wafer yield, a ratio of the number of non-defective chips to the total number of chips fabricated on a wafer, is reduced. The wafer yield is an important factor in determining the manufacturing cost of DRAM devices. Therefore, a need exists for a method of correcting defective memory cells in a semiconductor memory device to improve the wafer yield.
Generally, redundancy circuit is built in a semiconductor memory device to correct defective memory cells by replacing the defective memory cells with redundant memory cells. The redundancy circuit drives redundancy memory cell blocks arrayed in columns and rows and selects redundancy memory cells instead of defective cells. If a column and/or row address signal, which addresses a defective cell, is received, a redundancy memory cell is selected instead of the defective cell in a normal memory cell block.
A semiconductor memory device having a conventional column redundancy scheme is shown in FIG.
1
. Referring to
FIG. 1
, a semiconductor memory device
100
includes a plurality of sub memory blocks
110
,
120
,
130
and
140
and redundancy memory blocks
115
,
125
,
135
and
145
respectively adjacent to the sub memory blocks
110
,
120
,
130
and
140
. The bit lines of the sub memory blocks
110
,
120
,
130
and
140
and the bit lines of the redundancy memory blocks
115
,
125
,
135
and
145
are controlled by a column decoder/redundancy control circuit
150
, so that they are connected to global data input output lines (hereinafter, referred to as GIO lines)
111
,
121
,
131
and
141
. The GIO lines
111
,
121
,
131
and
141
are coupled to an input output pad unit
160
through reading sense amplifier/writing drivers
114
,
124
,
134
and
144
, respectively, and carry data to be written to or read from the memory cells of a memory cell block selected among the sub memory blocks
110
,
120
,
130
and
140
or redundancy memory blocks
115
,
125
,
135
and
145
.
FIG. 2
shows the GIO line
141
connected to the sub memory block
140
and the redundancy memory block
145
of
FIG. 1
, in greater detail. Referring to
FIG. 2
, the bit lines BL of the sub memory block
140
and the bit lines RBL of the redundancy memory block
145
are connected to GIO<i> lines (where i=0, 2, 4, 6) via a column selection circuit
240
. The column selection circuit
240
is part of the column decoder/redundancy control circuit
150
of
FIG. 1
, which is described below in connection with the reading operation of the semiconductor memory device. The column selection circuit
240
includes first, second and third selection units
241
,
242
and
243
. The first selection unit
241
transmits data in the bit lines (BL) of the sub memory block
140
to the second selection unit
242
in response to a bank selection signal BDCAij. The second selection unit
242
transmits data in the bit lines (BL) of the sub memory block
140
from the first selection unit
241
to local data input output lines LIO<i> (where i=0, 2, 4, 6) by selectively responding to a column selection signal CSL<j> (where j is an integer from 0 to m). The third selection unit
243
transmits data on the local data input output lines LIO<i> (where i=0, 2, 4, 6) to the GIO lines in response to the bank selection signal BDCAij.
When a defective cell occurs in the sub memory block
140
, it is replaced with a memory cell in the redundancy memory block
145
. That is, a bit line connected to the defective cell is replaced with a bit line RBL in the redundancy memory block
145
. In order to achieve this, the column selection circuit
240
further includes first and second redundancy selection units
244
and
245
. The first redundancy selection unit
244
transmits data in the bit lines RBL of the redundancy memory block
145
to the second redundancy selection unit
245
in response to the bank selection signal BDCAij. The second redundancy selection unit
245
transmits data in the bit lines RBL of the redundancy memory block
145
received from the first redundancy selection unit
244
to the local data input output lines LIO<i> (where i=0, 2, 4, 6) by selectively responding to a redundancy column selection signal RCSL<j> (where j is an integer from 0 to n). The redundancy column selection signal RCSL<j> (where j is an integer from 0 to n) is generated corresponding to the column selection signal CSL<j> (where j is an integer from 0 to m). The data on the bit lines RBL of the redundancy memory block
145
from the local data input output lines LIO<i> (where i=0, 2, 4, 6) is transmitted to the GIO<i> lines (where i=0, 2, 4, 6) via the third selection unit
243
. In this way, the detective cell of the sub memory block
140
is replaced with a memory cell of the redundancy memory block
145
.
However, in the conventional column redundancy scheme, the redundancy memory blocks
115
,
125
,
135
and
145
are required to correct defective cells in the sub memory blocks
110
,
120
,
130
and
140
. Thus, the number of memory cells in the redundancy memory blocks
115
,
125
,
135
and
145
increase to improve redundancy efficiency of a semiconductor memory device, so that the size of the semiconductor memory device increases.
Since each of the redundancy memory blocks
115
,
125
,
135
and
145
is corresponding to each of the sub memory blocks
110
,
120
,
130
and
140
in the conventional redundancy scheme, the redundancy efficiency is limited to a single sub memory block. Even if the adjacent sub memory blocks share the local data input output lines LIO<i> (where i=0, 2, 4, 6), the redundancy efficiency of a single redundancy memory block is limited to two sub memory blocks.
Therefore, a need exists for a redundancy scheme capable of improving redundancy efficiency without increasing the size of a semiconductor memory device.
SUMMARY OF THE INVENTION
To solve the above and other problems, it is an object of the present invention to provide a redundancy scheme capable of improving redundancy efficiency without increasing the size of a semiconductor memory device.
The above and other objects are achieved by a semiconductor memory device having a redundancy scheme according to the present invention. As a first embodiment of the present invention, a semiconductor memory device preferably includes a plurality of sub memory blocks having a plurality of memory cells; a redundancy memory block having a plurality of redundancy memory cells; a global data input output line for carrying data of selected memory cells of a sub memory block; a redundancy global data input output line for carrying data of selected redundancy memory cells of the redundancy memory block; and a switch for switching the global data input output line to the redundancy global data input output line if a memory cell connected to the global data input output line is defective.
As a second embodiment of the present invention, a semiconductor memory device preferably includes a plurality of sub memory blocks having a plurality of memory cells; local redundancy memory blocks having a plurality of local redundancy memory cells, each of the local redundancy memory blocks being adjacent to each of the sub memory blocks; a red

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