Semiconductor memory device having clamping circit for suppressi

Details Semiconductor memory device having clamping circit for suppressi Semiconductor memory device having clamping circit for suppressi

1991-06-04

1994-11-29

Ham, Seungsook

Static information storage and retrieval

Read/write circuit

Including signal clamping

36518909, G11C 702, G11C 1140

Patent

active

053696131

ABSTRACT:
The semiconductor memory device according to the present invention includes a memory cell array consisting of a plurality memory cells provided in array form and a plurality of bit lines and word lines connected respectively to the plurality of memory cells, I/O lines consisting of a first wiring and a second wiring connected to a predetermined number of bit lines out of the plurality of the bit lines via a selection circuit, and a clamping circuit which is activated at the time of read and includes a first device which connects the first wiring and the second wiring when the potential of the first wiring exceeds the potential of the second wiring by more than a predetermined voltage value, and a second device which connects the first wiring and the second wiring when the potential of the second wiring exceeds the potential of the first wiring by more than the predetermined voltage. Thus, even when a potential drop is generated in the I/O lines during the transition period, a marked drop in the potential of one of the wirings can be prevented by the clamping operation between the two wirings that constitute the I/O lines. Accordingly, it is possible to prevent the destruction of data in the memory cells, and to enhance the reading speed of the next data because of the small value of the potential drop of the wiring.

REFERENCES:
patent: 4376987 (1983-03-01), Hsia
patent: 4740926 (1988-04-01), Takemae et al.
patent: 4785427 (1988-11-01), Young
patent: 4825413 (1989-04-01), Tran
patent: 5047984 (1991-09-01), Monden

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