Semiconductor memory device having circuit array structure for f

Details Semiconductor memory device having circuit array structure for f Semiconductor memory device having circuit array structure for f

1996-07-01

1997-08-12

Nelms, David C.

Static information storage and retrieval

Interconnection arrangements

365 51, 36523003, G11C 506

Patent

active

056572654

ABSTRACT:
A semiconductor memory device includes at least four memory cell array blocks, each having an array of memory cells, row and column decoders for selecting a memory cell designated by a row and column address, an I/O line for inputting/outputting data of the memory cell array block, and an I/O driver connected to the I/O line for selectively driving data to/from a selected memory cell. A first data line transmits the data, being connected between the I/O driver of one memory cell array block and the I/O driver of another memory cell array block oppositely arranged with respect to a central portion of the semiconductor memory device. A second data line transmits the data by connecting the first data lines of at least two memory cell array blocks disposed adjacent to each other. A data sense amplifier, connected to the second data line, senses and amplifies the data, and a data output unit, connected to the data sense amplifier, outputs the amplified data to an external lead frame. Therefore, the present invention has an advantage in that a relatively small layout area in required and a relatively low amount of power is consumed.

REFERENCES:
patent: 5361223 (1994-11-01), Inoue et al.
patent: 5363339 (1994-11-01), Fujita
patent: 5369619 (1994-11-01), Ohba
patent: 5499215 (1996-03-01), Hatta
patent: 5535153 (1996-07-01), Saeki

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