Semiconductor memory device having cell isolation structure

Details Semiconductor memory device having cell isolation structure Semiconductor memory device having cell isolation structure

1994-11-03

1996-05-28

Limanek, Robert P.

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257305, 257306, 257395, H01L 27108, H01L 2976

Patent

active

055214070

ABSTRACT:
The first element separation oxide film consisting of a plurality of line-shaped portions parallel to the bit line is formed on the surface of the P-type silicon substrate. The first and second trenches are formed in that portion of the P-type silicon substrate which is located between an adjacent pair of line-shaped portions of the first element separation oxide film such that both sides of the trenches come in contact with the first element separation oxide film. A sheath plate capacitor is formed in each of the trenches. The second element separation oxide film having a thickness less than that of the first element separation oxide film is formed on that portion of the surface of the P-type silicon substrate which is located between the first and second trenches.

REFERENCES:
patent: 4422092 (1983-12-01), Guterman
patent: 4855953 (1989-08-01), Tsukamoto et al.
patent: 4894697 (1990-01-01), Chin et al.
patent: 4918502 (1990-04-01), Kaga et al.
patent: 5237528 (1993-08-01), Sunami
patent: 5258321 (1993-11-01), Shimizu et al.
Toru Kaga et al.; IEEE Transactions on Electron Devices, dated Aug. 8, 1988, vol. 35, No. 8, "Half-V.sub.cc Sheath-Plate Capacitor DRAM Cell with Self-Aligned Buried Plate Wiring" pp. 1257-1263.

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