Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-12-28
2003-03-18
Lee, Eddie (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S301000, C257S303000, C257S306000, C257S308000
Reexamination Certificate
active
06534810
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a semiconductor memory device and, more particularly, to a semiconductor memory device having a compact cell size and a method for the manufacture thereof by forming a capacitor structure over a transistor and connecting each other indirectly.
DESCRIPTION OF THE PRIOR ART
As is well known, a dynamic random access memory (DRAM) having memory cells comprising a transistor and a capacitor achieve higher degrees of integration mainly by down-sizing the memory cells through miniaturization of the components. However, despite the high levels of integration that have been achieved to date, there is a continuing demand for further downsizing of the memory cell area.
To meet this demand, therefore, several methods have been proposed, including a trench type or a stack type capacitor, which uses a three-dimensional structure to reduce the cell area required to form the capacitor. However, the process of manufacturing a three-dimensional capacitor structure is long, tedious and complicated, and consequently involves high manufacturing cost. Therefore, a strong demand exists for a new memory device that can reduce the cell area necessary to hold the requisite volume of information without requiring complex manufacturing steps.
In attempting to meet this requirement, proposals have been to use a ferroelectric random access memory (FeRAM) in which a thin film capacitor having ferroelectric properties, such as strontium bithmuth tantalate (SBT) or lead zirconate titanate (PZT), is used as the capacitor dielectric in place of the conventional silicon oxide or silicon nitride films.
In
FIG. 1
, there is shown a cross sectional view setting forth a conventional semiconductor memory device
100
for use as a FeRAM. The semiconductor memory device
100
includes an active matrix
8
incorporating a transistor, a capacitor structure
22
having a bottom electrode
15
, a capacitor dielectric thin film
16
and a top electrode
17
. Also shown in
FIG. 1
are an isolation region
11
, a word line
12
, diffusion regions
13
, a first insulating layer
14
, a second insulating layer
18
, a metal interconnection
19
A and a bit line
19
B.
The process for manufacturing the conventional semiconductor memory device
100
begins with the preparation of the active matrix
8
having the silicon substrate
10
, the transistor formed thereon as a selective transistor, the isolation region
11
and the first insulating layer
14
formed on the transistor and the isolation region
11
. The transistor includes the diffusion regions
13
as a source and a drain.
In subsequent steps, the bottom electrode
15
, the capacitor thin film
16
and the top electrode
17
, are formed sequentially on the first insulating layer
14
of the active matrix
8
. The capacitor thin film
16
comprises a ferroelectric material. The bottom and top electrodes
15
,
17
are deposited using a sputter process and the capacitor thin film
16
is formed using a spin-on coating process. The electrodes
15
,
17
and the capacitor thin film
16
are then patterned and etched to form a predetermined configuration.
In a next step, the second insulating layer
18
is formed on top of the active matrix
8
and the capacitor structure
22
using a plasma chemical vapor deposition (CVD). Openings are then formed in the second insulating layer
18
and the first insulating layer
14
of the active matrix
8
at positions over the diffusion regions
13
of the transistor and the top electrode
15
of the capacitor structure
22
by reactive ion etching (RIE).
Finally, the metal interconnection layer
19
A is formed over the entire surface and is patterned and etched to form the bit line
19
B and a metal interconnection
19
A, as shown in FIG.
1
.
One of the major shortcomings of the above-described semiconductor memory device
100
and the related method for manufacturing such devices is the difficulty in reducing the cell area because the capacitor structure
22
is not vertically aligned with the associated transistor and thus consumes additional surface area.
Referring to
FIG. 2
, there is shown a cross sectional view setting forth another conventional semiconductor memory device
200
for use as FeRAM, that overcomes the noted shortcomings of the semiconductor memory device
100
. The semiconductor memory device
200
includes an active matrix
31
incorporating a transistor, an isolation region
21
, an insulating layer
24
, a word line
22
, a bit line
25
, a conductive plug
26
, e.g., a polysilicon plug, a barrier layer
27
for protecting the capacitor
32
during high temperature thermal treatment such as annealing and crystallization, and a capacitor structure
32
having a bottom electrode
28
, a capacitor dielectric thin film
29
and a top electrode
30
.
In comparison with the semiconductor memory device
100
, the memory device
200
has the advantage of reduced cell size. That is, the capacitor structure
32
is positioned over the conductive plug
26
so that it is possible to reduce the cell area in comparison with the memory device
100
depicted in FIG.
1
. However, since the capacitor structure
32
is in direct contact with the conductive plug
26
, the memory device
200
has a drawback in that a barrier layer is typically needed to protect against Si inter-diffusion phenomenon during high thermal treatment. And the memory device
200
has another drawback in that the manufacturing cost is increased because the polysilicon plug is formed using a chemical mechanical polishing (CMP) method. Furthermore, the memory device
200
has still another drawback in that the step height and aspect ratio for forming the storage node is increased to a degree that renders it difficult to obtain good step coverage.
SUMMARY OF THE INVENTION
It is, therefore, an object of the present invention to provide a semiconductor memory device having a reduced cell area by forming capacitor structure at a position over the corresponding transistor and connecting them to each other indirectly.
It is another object of the present invention to provide a method for manufacturing a semiconductor memory device having a compact cell size by forming a capacitor structure at a position over the corresponding transistor and connecting them to each other indirectly.
In accordance with one aspect of the present invention, there is provided a semiconductor memory device, comprising: an active matrix provided with a semiconductor substrate, a transistor formed on the semiconductor substrate and isolation regions for isolating the transistor; a first metal pattern formed on top of the active matrix and extending outside the transistor; a capacitor structure formed over the transistor; a barrier layer formed on top of the capacitor structure to thermally stabilize the capacitor; and a second metal pattern formed on top of the capacitor structure for electrically connecting the capacitor structure to the transistor through the first metal and second metal patterns.
In accordance with another aspect of the present invention, there is provided a method for manufacturing a semiconductor memory device, the method comprising the steps of: a) preparing an active matrix including a semiconductor substrate, a transistor formed on top of the semiconductor substrate and a first insulating layer formed around the transistor; b) forming a first metal layer and patterning and etching the first metal layer to form a first predetermined configuration to obtain a first metal pattern for electrically connecting the transistor thereto; c) forming a second insulating layer on top of the first metal pattern; d) forming a capacitor structure on the second insulating layer at a position over the transistor; e) forming a barrier layer on top of the capacitor structure and patterning and etching the barrier layer into a second predetermined configuration to make the capacitor thermally stabilize; and f) forming a second metal layer and patterning and etching the second metal layer into a third predetermined configuration
Fenty Jesse A.
Hyundai Electronics Industries Co,. Ltd.
Lee Eddie
Pillsbury & Winthrop LLP
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