Semiconductor memory device having cache function

Details Semiconductor memory device having cache function Semiconductor memory device having cache function

1996-02-16

1999-08-24

Swann, Tod R.

Electrical computers and digital processing systems: memory

Storage accessing and control

Specific memory composition

711118, 36518905, G06F 1200

Patent

active

059436816

ABSTRACT:
A cache DRAM includes a main memory, a main cache memory for storing data which is accessed at a high frequency out of data stored in the main memory, a main tag memory for storing an address in the main memory of the data stored in the main cache memory, a subcache memory for always receiving data withdrawn from the main cache memory for storage and supplying the stored data to the main memory when the main memory is in a ready state, and a subtag memory for storing an address in the main memory of the data stored in the subcache memory. Since the subcache memory serves as a buffer for data to be transferred from the main cache memory to the main memory, the main cache memory withdraws data to the subcache memory even if the main memory is in a busy state.

REFERENCES:
patent: 5226139 (1993-07-01), Fujishima
patent: 5261066 (1993-11-01), Jouppi
patent: 5305280 (1994-04-01), Hayano
patent: 5359722 (1994-10-01), Chan
patent: 5386547 (1995-01-01), Jouppi
patent: 5509132 (1996-04-01), Matsuda
patent: 5619676 (1997-04-01), Fukuda
Katsumi Dosaka et al, A 100MHz 4Mb Cache DRAM with Fast Copy-Back Scheme, IEEE International Solid-State Circuits Conference, 1992, pp. 148-149.
Akira Yamazaki et al, A Current Operating CDRAM for Low Cost Multi-Media, pp. 61-62.
The Cache Memory Book, Handy, 1993, ISBN 0-12-322985-5.

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