Semiconductor memory device having breaker associated with addre

Details Semiconductor memory device having breaker associated with addre Semiconductor memory device having breaker associated with addre

1991-06-28

1994-02-08

Grimm, Siegfried H.

Static information storage and retrieval

Read/write circuit

Bad bit

365 96, 36523006, 371 111, G11C 700, G11C 2900

Patent

active

052854175

ABSTRACT:
A semiconductor memory device comprises regular memory cells arranged in rows and columns, word lines respectively coupled to the rows of the regular memory cells, a row address decoding circuit responsive to external address bits for designating one of the word lines, word line driving circuits respectively associated with the word lines and driving one of the word lines under the control of the row address decoding circuit, and a row of redundant memory cells with which one of the rows of the regular memory cells is replaced upon discovering a defective memory cell incorporated therein, wherein breakable elements are coupled between the row address decoding circuit and the word line driving circuits and one of the breakable elements associated with the row with the defective memory cell is broken so that any data bit is never read out from the defective memory cell even if the external address bits designate the defective memory cell.

REFERENCES:
patent: 4587638 (1986-05-01), Isobe et al.
patent: 4720817 (1988-01-01), Childers
patent: 4985866 (1991-01-01), Nakaizumi
patent: 4987560 (1991-01-01), Hamano et al.

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