Static information storage and retrieval – Read/write circuit – Including level shift or pull-up circuit
Reexamination Certificate
2002-07-10
2004-07-27
Ho, Hoai (Department: 2818)
Static information storage and retrieval
Read/write circuit
Including level shift or pull-up circuit
C365S185180, C365S233500
Reexamination Certificate
active
06768688
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device. More particularly, the present invention relates to boosting voltage of a word line of a semiconductor memory device.
2. Description of the Background Art
In recent years, demand for nonvolatile semiconductor memory devices increases. As such a semiconductor memory device, an electrically erasable and programmable read only memory (hereinafter referred to as EEPROM) such as a flash memory is known. In EEPROM, a plurality of potentials that are different from a potential of power supply supplied from outside of EEPROM are generated, a voltage of a word line are boosted by means of these potentials, so that EEPROM performs operations such as electrically writing, reading, erasing, and the like of data.
Japanese Laid-Open Patent Publication No. 6-28876 (Japanese Patent No. 3161052) discloses a configuration of a nonvolatile semiconductor memory device which boosts a voltage of a word line. More specifically,
FIG. 1A
is a conventional circuit diagram in which the voltage of a word line is boosted.
FIG. 1B
is a timing chart of the circuit in FIG.
1
A. An operation of the circuit will be described below with reference to FIG.
1
A. Whether the voltage of the word line is boosted or not, i.e., whether the word line is selected or not is determined by examining whether all internal row address signals are at high levels or not. When at least one of the internal row address signals is at low level, potential of node
89
becomes ground level. In this case, the word line is in non-selected state. On the other hand, when all the internal row address signals are at high levels, the potential of node
89
is equal to that of node
88
, and the word line is in selected state.
Before the word line is selected to boost the voltage of the word line, the circuit receives from an address transition detector (ATD) circuit (not shown) a high-level ATD signal that representing that an address to be accessed is subjected to transition. As a result, an output from inverter
86
becomes low level, and charge of capacitor
87
connected to node
88
is started. This charging is performed in a period of time in which ATD signal is at high level. The operation timing is as shown in FIG.
1
B. When ATD signal becomes low level, boosting the voltage of the word line is started. At this time, the voltage level of node
88
reaches Vcc which is equal to power supply voltage, and the charging has been completed. Therefore, the voltage of the word line can be boosted.
In order to increase speed of an access operation of the semiconductor memory device, the time required to charge capacitor
87
must be shortened. In other words, the period of time in which ATD signal is at high level must be shortened. However, when the period of time is shortened, the time required to charge capacitor
87
is insufficient, and a boost operation cannot be normally performed.
SUMMARY OF THE INVENTION
It is an object of the present invention to perform a normal boost operation while increasing the speed of an access operation in a semiconductor memory device.
According to an aspect of the present invention, the semiconductor memory device includes: a plurality of memory cells; a plurality of word lines to which voltages are applied to select the plurality of memory cells; a decoder that selects one of the plurality of word lines based on an address signal representing an address of one of the plurality of memory cells to be accessed; a control circuit that outputs an activated control signal and an deactivated control signal according to a transition of the address signal; and a booster that has a plurality of booster circuits including first booster circuit and second booster circuit. The first booster circuit being connected to the decoder and supplying boosted voltage to a selected word line based on the activated control signal. The second booster circuit being input the deactivated control signal.
When each of the plurality of booster circuits are controlled to be activated/deactivated, while one booster circuit is in a boost operation for a word line, the other booster circuit can perform charging. Since an apparent charging time can be shortened while sufficient charging for boosting is performed, high speed access to the memory cell can be realized. In particular, since the plurality of booster circuits are alternatively activated/deactivated, charging is normally completed every timing at which address transition occurs, and boosted voltage can be supplied to a word line.
The second booster circuit may charge, based on the deactivated control signal, an internal node of the second booster circuit up to a voltage obtained before the boosted voltage is output. According to the operation, an apparent charging time is further shortened, and high speed access to the memory cell can be realized.
The each of a plurality of booster circuits may include a plurality of capacitor elements, a first circuit that charges the plurality of capacitor elements when the control signal is deactivated; and a second circuit that outputs the boosted voltage obtained by series connection of the plurality of charged capacitor elements when the control signal is activated. In this manner, a boost operation and a charging operation can be switched to each other. According to this configuration, an apparent charging time can be shortened while sufficient charging for boosting is performed.
The semiconductor memory device may further include a detection circuit that detects the transition of the address signal to output a detection signal, the control circuit may have a counter circuit that counts transitions of the detection signal output from the detection circuit to switch the activated control signal and the deactivated control signal. According to this configuration, while one booster circuit is in a boost operation for a word line, the other booster circuit can perform charging.
REFERENCES:
patent: 6141262 (2000-10-01), Sudo
patent: 6147923 (2000-11-01), Nakano
patent: 6-28876 (1994-02-01), None
patent: 7-46825 (1995-02-01), None
Ohm-sha, Electronic Engineering Pocket Book, 3rd Edition, 1981 (w/Partial English Translation).
Ho Hoai
McDermott Will & Emery LLP
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