Static information storage and retrieval – Read/write circuit – Including level shift or pull-up circuit
Reexamination Certificate
2001-06-08
2003-04-08
Ho, Hoai (Department: 2818)
Static information storage and retrieval
Read/write circuit
Including level shift or pull-up circuit
C365S149000, C365S230030
Reexamination Certificate
active
06545918
ABSTRACT:
CLAIM OF PRIORITY
This application claims the benefit of priority under 35 U.S.C. §119(a) of Korean Patent Application No. 2000-32390 filed on Jun. 13, 2000. A certified copy of the Korean Patent Application is submitted concurrently herewith.
BACKGROUND
1. Field of the Invention
The present invention relates to semiconductor memory devices, and more particularly, a semiconductor memory device having a voltage stabilization circuit that is capable of stabilizing a boosted voltage level.
2. Description of the Related Art
In dynamic random access memories (DRAMs), a boosted voltage, which is a voltage higher than the power supply voltage by a threshold voltage amount or higher, is used for controlling cell transistors. Boosted voltage is used because it takes a relatively long time to transmit the charge stored in a cell capacitor to the bit line, and to transmit a sufficient voltage of a bit line to a cell capacitor while storing data. Therefore, a boosted voltage generation circuit is one of the essential circuits in a DRAM.
During the operation of a memory formed of silicon, a boosted voltage Vpp depends on the number of circuits, the amount of charge used by each circuit, and the performance of each circuit in compensating for the amount of charge that is used. Circuits used for generating the boosted voltage Vpp include a boosted voltage Vpp pump and an active kicker. However, when the compensation performance of the pump and active kicker are fixed, the level of boosted voltage Vpp changes or fluctuates. In other words, in a case where a small amount of boosted voltage Vpp is used, the level of the boosted voltage Vpp increases when the amount of charge compensated for is larger than the amount of boosted voltage Vpp used. In contrast, in a case where a large amount of boosted voltage Vpp is used, the level of boosted voltage Vpp decreases when the amount of charge compensated for is smaller than the amount of the boosted voltage Vpp used.
When a memory cell array comprised of block units is activated in a DRAM, a boosted voltage Vpp load varies depending on the position of the block unit in the cell array. The load varies depending on whether a block unit located near the edge (e.g., outer) of the cell array is selected, or a block unit located in the interior (e.g., inside) of the cell array is selected. For example, for a memory device comprised of four cell array blocks, depending on the location of the activated cell array block, the maximum amount of boosted voltage Vpp used (e.g., the maximum amount of charge consumption) can be twice as large as the minimum amount of charge consumption.
FIG. 1
illustrates a main path through which a boosted voltage Vpp is applied when a row address strobe (RAS) is active in a conventional DRAM. Reference numerals
10
and
11
designate a first cell array block and a second cell array block, respectively. Reference numerals
14
and
16
designate selection control signal Pxi drivers used in selecting a cell array block. Reference numeral
12
denotes a broken line, which designates an output line of selection control signal Pxi driver
14
. Reference numeral
13
denotes a thick solid line, which designates an output line of selection control signal Pxi driver
16
.
Signals Px
0
a
and Px
2
a
can be used to select selection control Pxi drivers
14
and
16
, respectively, and are generated based on an address. The selected selection control signal Pxi driver (e.g., selection control signal Pxi driver
14
or selection control signal Pxi driver
16
) outputs a boosted voltage Vpp to a word line through a sub-word line driver
15
,
17
, or
18
. The structure and operation of selection control signal Pxi drivers
14
and
16
, and sub-word line drivers
15
,
17
, and
18
are apparent to those skilled in the art, and thus, further descriptions of the components are not provided.
DRAMs are designed such that two adjacent cell array blocks share a control signal Pxi driver and an output line. For example, as depicted in
FIG. 1
, two adjacent cell array blocks, first cell array block
10
and second cell array block
11
, share selection control signal Pxi driver
16
and output line
13
. However, selection control signal Pxi driver
14
, located at the edge of the memory cell array, and output line
12
are used only by first cell array block
10
, which is located at the edge. Accordingly, the length or load of output line
12
of selection control signal Pxi driver
14
is approximately one-half the length or load of output line
13
of selection control signal Pxi driver
16
.
During the DRAM's operation, the discrepancy in the length of the output lines cause the amount of boosted voltage Vpp used by selection control signal Pxi driver
14
and output line
12
, which are located at the edge of the memory cell array, to be approximately one-half of the amount of boosted voltage Vpp used by selection control signal Pxi driver
16
and output line
13
, which are shared by two adjacent cell array blocks. The differing amount of boosted voltage Vpp used causes the boosted voltage Vpp level to fluctuate during the DRAM's operation. In DRAMs, fluctuating boosted voltage Vpp levels are undesirable.
FIG. 2
illustrates a diagram that explains the different amounts of boosted voltage used during a precharge in a conventional DRAM. Reference numerals
20
,
21
,
22
, and
23
designate a first through fourth cell array block, respectively. Reference numerals
24
,
25
, and
26
designate shared sense amplifiers, where each shared sense amplifier is shared by two adjacent cell array blocks, Reference numerals
27
,
28
,
29
,
30
,
31
, and
32
designate isolation transistor units.
As depicted in
FIG. 2
, in a memory device using a shared sense amplifier, a bit line of an inner cell array block, for example, second cell array block
21
, is sensed by two shared sense amplifiers
24
and
25
. Shared sense amplifier
24
is positioned along the upper side of second cell array block
21
and shared sense amplifier
25
is positioned along the lower side of second cell array block
21
. In contrast, a bit line of an outer or edge cell array block, for example, first cell array block
20
, is sensed by a single shared sense amplifier
24
.
When sensing a bit line of one of two adjacent cell array blocks, the isolation transistor unit corresponding to the bit line of the cell array block that is not being sensed is turned off, effectively blocking the bit line from the shared sense amplifier. For example, when sensing a bit line of an outer cell array block (e.g., first cell array block
20
), isolation transistor unit
28
is turned off to block a bit line of adjacent second cell array block
21
from shared sense amplifier
24
. As another example, when sensing a bit line of an inner cell array block (e.g., second cell array block
21
), isolation transistor unit
27
is turned off to block a bit line of adjacent first cell array block
20
, and isolation transistor unit
30
is turned off to block a bit line of adjacent third cell array block
22
.
During a precharge, which typically occurs after RAS becomes active, a blocked bit line is reconnected to a shared sense amplifier. Boosted voltage Vpp is used to reconnect a blocked bit line. For an outer cell array block, a bit line of one adjacent cell array block is reconnected to a shared sense amplifier during the precharge. For an inner cell array block, two bit lines, one from each adjacent cell array block, are connected to its respective shared sense amplifier during the precharge. The amount of boosted voltage Vpp used during the precharge is proportional to the number of bit lines reconnected during the precharge. Accordingly, during precharge, the amount of boosted voltage Vpp used in an outer cell array block is approximately one-half the amount of boosted voltage Vpp used in an inner cell array block.
In conventional semiconductor memory devices having shared circuits to reduce the size of a cell array block, the amount of boosted voltage Vpp used varies depend
Harness Dickey & Pierce PLC
Ho Hoai
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