Semiconductor memory device having bit line pairs each divided i

Details Semiconductor memory device having bit line pairs each divided i Semiconductor memory device having bit line pairs each divided i

1990-12-04

1993-11-16

LaRoche, Eugene R.

Static information storage and retrieval

Read/write circuit

For complementary information

365205, 365208, G11C 700

Patent

active

052629929

ABSTRACT:
Memory cells incorporated in a semiconductor memory device are arranged in matrix and coupled to bit line pairs, respectively, wherein each of the columns of the memory cells is divided into memory blocks coupled to bit line sections of the associated bit line pair and gate circuits accompanied with sense amplifier circuits are respectively coupled between the bit line sections for transferring a data bit through the associated gate circuits or, alternatively, data bits through difference amplifications of the associated sense amplifier circuits, thereby enhancing propagation of the data bits because the parasitic capacitance coupled to the bit line pairs are shared by the associated sense amplifier circuits.

REFERENCES:
patent: 4899316 (1990-02-01), Nagami
patent: 4947377 (1990-04-01), Hannai
patent: 5012450 (1991-04-01), Mattausch et al.
patent: 5014246 (1991-05-01), Komatsu et al.
patent: 5016224 (1991-05-01), Tanaka et al.
patent: 5029137 (1991-07-01), Hoshi
patent: 5097450 (1992-03-01), Toda et al.
IBM Technical Disclosure Bulletin, vol. 31, No. 5, Oct. 1988, New York US, pp. 327-328.

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