Semiconductor memory device having bit line equalizer in...

Details Semiconductor memory device having bit line equalizer in... Semiconductor memory device having bit line equalizer in...

2006-12-29

2009-02-24

Hoang, Huan (Department: 2827)

Static information storage and retrieval

Read/write circuit

Flip-flop used for sensing

C365S202000, C365S203000

Reexamination Certificate

active

07495983

ABSTRACT:
A semiconductor memory device includes at least one cell array and first and second bit line sense amplifying units. A cell array includes a plurality of bit line pairs and a plurality of bit line equalizers connected to each other through a signal line. Each bit line equalizer equalizes a corresponding bit line pair. The first and the second bit line sense amplifying units are alternately connected to the bit line pairs and receive respective bit line equalization signals.

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Korean Office Action issued in corresponding Korean Patent Application No. KR 2006-0059070, dated May 31, 2007.
Korean Office Action, issued in corresponding Korean Patent Application No. 10-2006-0059070, dated on Sep. 13, 2007.

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