Semiconductor memory device having bipolar transistor

Details Semiconductor memory device having bipolar transistor Semiconductor memory device having bipolar transistor

1995-06-05

1996-08-13

Yoo, Do Hyun

Static information storage and retrieval

Read/write circuit

For complementary information

365177, 365203, 257370, 257378, G11C 700

Patent

active

055463452

ABSTRACT:
In a memory cell array, memory cells are formed in a matrix. Bit lines are formed to be connected to prescribed memory cells. Emitters of bipolar transistors are connected to bit lines. Bipolar transistors have their bases connected to each other, and further to precharge signal control means. Collector regions of bipolar transistors are connected to a power supply node. Bipolar transistors have a base region formed by introducing a p type impurity to the entire main surface of the semiconductor substrate, and n type impurity concentration included in the collector region immediately below the base region is at most 5.times.10.sup.18 cm.sup.-1. Consequently, a semiconductor memory device having a bipolar transistor which is capable of high speed operation and having high reliability can be manufactured at low cost.

REFERENCES:
patent: 5392243 (1995-02-01), Hakamura
patent: 5396462 (1995-03-01), Kaneko
patent: 5418748 (1995-05-01), Monden
patent: 5487044 (1996-01-01), Kawaguchi et al.
patent: 5495120 (1996-02-01), Honda
Paul R. Gray and Robert G. Meyer, Analysis and Design of Analog Integrated Circuits, Second Edition, Chapters 2.3-2.4, pp. 88-113.

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