Semiconductor memory device having at least two layers of...

Details Semiconductor memory device having at least two layers of... Semiconductor memory device having at least two layers of...

2000-05-15

2001-04-24

Nelms, David (Department: 2818)

Static information storage and retrieval

Systems using particular element

Flip-flop

C257S903000

Reexamination Certificate

active

06222758

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device having at least two layers of bit lines.
2. Description of the Background Art
In recent years, a T-shaped bit line configuration formed of at least two layers of bit lines has been employed in semiconductor memory devices, especially in static random access memories (SRAM). Such a configuration is disclosed, for example, in Japanese Patents Laying-Open Nos. 4-228188 and 7-183396.
FIG. 11
shows configurations of a memory cell array and its peripheral circuits of a semiconductor memory device, which is essentially identical to
FIG. 13
of Japanese Patent Laying-Open No. 7-183396.
Referring to
FIG. 11
, memory cells
1
a
-
1
c
are partitioned by a broken line. Note that this line is only shown in the drawing for convenience, and there is no such partition in an actual product.
FIG. 11
includes squares other than memory cells
1
a
-
1
c
. These squares, identical to memory cells
1
a
-
1
c
but having no reference characters, also show memory cells. Likewise, for other patterns representing various components through the drawings, those having the same shapes represent the same components, and only representative members are labeled for purposes of presentation.
Bit lines in the first layer (hereinafter, first-layer bit lines)
2
a
and
2
b
are connected to the same memory cell, forming a bit line pair. Both bit lines
2
a
and
2
b
are also connected to bit line peripheral circuits
4
a
and
4
c.
A word line
3
is connected to memory cells
1
a
,
1
c
, . . . , and to a row decoder
5
. Of the bit lines in the second layer (hereinafter, second-layer bit lines)
22
a
and
22
b
, bit line
22
a
is connected via a contact hole
12
a
to first-layer bit line
2
a
, and bit line
22
b
is connected via a contact hole
12
b
to first-layer bit line
2
b
. Both bit lines
22
a
and
22
b
are connected to a bit line peripheral circuit
4
b.
Generally, the direction along which first-layer bit lines
2
a
,
2
b
extend is called a column direction, while the direction along which word line
3
extends is called a row direction. Memory cells are arranged in the row and column directions, forming a memory cell array.
FIG. 12
shows memory cells within the memory cell array corresponding to a region A of
FIG. 11
, with three memory cells in the row direction and two memory cells in the column direction being selected.
FIG. 12
illustrates the pattern of the bit lines in the first and second layers.
Memory cell regions
31
a
-
31
c
include first-layer bit lines
32
a
-
32
d
formed of a first metal interconnection layer, and second-layer bit lines
52
a
,
52
b
formed of a second metal interconnection layer. Second-layer bit lines
52
a
,
52
b
are connected via through-holes
42
a
,
42
b
as contact holes, to firstlayer bit lines
32
a
,
32
b
, respectively. Through-holes
42
a
and
42
b
are provided in respective memory cell regions
31
a
and
31
b.
FIG. 13
illustrates an example of a memory cell pattern commonly used in an SRAM. Specifically,
FIG. 13
shows the memory cell pattern located underneath the first-layer bit lines, corresponding to memory cell region
31
a
of FIG.
12
.
This memory cell pattern includes: separating insulation films
61
a
-
61
c
; active layers
62
a
-
62
j
; layers including polycrystalline silicon (hereinafter, referred to as “polysilicon layers”)
63
a
-
63
c
; third metal interconnection layers
65
a
-
65
d
; and first contacts
64
a
-
64
d
coupling active layers
62
a
-
62
j
and third metal interconnection layers
65
a
-
65
d.
Here, metal interconnection layer
65
a
is a GND interconnection, and metal interconnection layer
65
b
is a Vcc interconnection. First contacts
64
a
,
64
b
are called GND contacts, and first contacts
64
c
,
64
d
are called Vcc contacts. Further, this memory cell pattern includes: a first contact
64
e
connecting the polysilicon layer and the third metal interconnection layer; and second contacts
66
a
,
66
b
connecting first-layer bit lines
32
a
,
32
b
and active layers
62
a
,
62
b
, respectively. Second contacts
66
a
,
66
b
are herein called bit line contacts.
Active layers
62
b
,
62
e
,
62
g
and
62
i
are the layers storing memory data of the memory cell. Active layers
62
b
and
62
g
are connected by third metal interconnection layer
65
c
, thereby forming one storage node portion. Active layers
62
e
and
62
i
are connected by third metal interconnection layer
65
d
, thereby forming the other storage node portion.
Active layers
62
c
,
62
f
are the layers connected via GND contacts
64
a
,
64
b
to GND interconnection
65
a
. Thus, they are called the GND active layers. Active layers
62
h
,
62
j
are connected via Vcc contacts
64
c
,
64
d
to Vcc interconnection
65
b
, and thus called the Vcc active layers. Polysilicon layer
63
a
corresponds to word line
3
of FIG.
11
.
Generally, memory cell regions have no boundary therebetween in an actual semiconductor memory device, and therefore, various definitions of boundaries can be considered. In any case, a memory cell region is a region which normally stores data of one bit.
Here, the size of the memory cell region in the row direction is defined as a minimal distance between the contact centers of GND contacts
64
a
and
64
b
taken in the row direction. It is specifically shown as CO in FIG.
13
. The size of the memory cell region in the column direction is defined as a minimal distance between the contact center of bit line contact
66
a
or
66
b
and the center line of Vcc interconnection
65
b.
In the case of
FIG. 12
, the size of the memory cell region in the row direction can be defined as the distance from the midpoint of bit lines
32
a
and
32
c
to the midpoint of bit lines
32
b
and
32
d.
In the conventional memory cells as shown in
FIGS. 12 and 13
, the size of the memory cell region in the row direction is normally limited by the size of the pattern underneath the first-layer bit lines.
However, if the miniaturization of the pattern underneath the first-layer bit lines advances beyond the miniaturization of the pattern of the metal interconnection layers, it is expected that the size of the memory cell region will be limited by the size of the first-layer bit lines.
In particular, in memories required to operate with even higher speed or system LSI devices incorporating logic and memories in the coming age, the double layered bit line configurations will be widely used. Thus, there is a high possibility that the bit lines in the first and second layers may limit the memory cell size.
Specifically, the size of the memory cell in the row direction may be affected or limited by the size of the portion connecting the bit lines in the first and second layers.
FIGS. 14 and 15
illustrate possible examples thereof.
To explain the limitation as described above in more detail, assume that the boundary of the memory cell regions in the row direction is defined as follows.
For the first memory cell and the second memory cell adjacent to each other in the row direction, their boundary is a line which passes the midpoint of the minimal gap between edges of a first-layer bit line in the first memory cell and a first-layer bit line in the second memory cell, and extends parallel to the column direction of the memory cell array.
Specifically, with reference to
FIG. 14
, the boundary on the left side is a line passing the midpoint between the edge of the projected portion of first-layer bit line
32
a
and the edge of first-layer bit line
32
c
, and extending parallel to first-layer bit line
32
c
. The boundary on the right side is a line passing the midpoint between the edge of the projected portion of first-layer bit line
32
b
and the edge of first-layer bit line
32
d
, and extending parallel to first-layer bit line
32
d.
With the assumption as described above, the size in the row direction of the memory cell region of
FIG. 14
will now be considered. Referring to
FIG. 14
, i

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