Semiconductor memory device having associative function

Static information storage and retrieval – Read/write circuit – Including signal comparison

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36518905, 36523008, G11C 700

Patent

active

049823795

ABSTRACT:
A semiconductor memory device includes a memory cell array having a plurality of memory cells and first, second, third and fourth data transferring portions. Tag information, key information and operand data applied to the first data transferring portion are sequentially transferred to the second data transferring portion, the third data transferring portion and the fourth data transferring portion. Any of the memory cells in the memory cell array are selected based on the key information, so that new tag information and operand data are read out from the selected memory cells. The inputted tag information and the tag information read out from the memory cell array are compared with each other by the comparison determining portion. When the information coincides with each other, the inputted key information, the new tag information, the new operand data and the inputted operand data are outputted to the exterior. When the information does not coincide with each other, the inputted tag information and the inputted operand data are written into the memory cell array.

REFERENCES:
patent: 4811294 (1989-03-01), Kobayashi et al.
Processings of 32nd National Conf. of Information Processing Society of Japan, 1986, "Memory Function in Data Flow Type Processor Q-P", pp. 221-222.
Electronic and Communication Society-Nov. 21, 1986; pp. 85-92, "Execution Control System of Data Driven Type Processor Q-P".
Technical Report of Institute of Electronic and Communication Engineers of Japan (1983), pp. 45-52.

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