Static information storage and retrieval – Read/write circuit – Plural use of terminal
Patent
1988-11-30
1990-06-12
Moffitt, James W.
Static information storage and retrieval
Read/write circuit
Plural use of terminal
36518908, 36523003, 365195, 36518905, G11C 700, G11C 1140
Patent
active
049339001
ABSTRACT:
A single chip semiconductor memory device having an arithmetic circuit to conduct plural kinds of arithmetic operations and a mask control circuit for inhibiting a substantial change in data in memory irrespective of the operations of the arithmetic circuit when it is brought into a masking state. The semiconductor memory device takes a preset operation mode for receiving from the outside a control signal for the arithmetic circuit and the mask control circuit. This control signal for the arithmetic circuit and the mask control circuit, which is given to the semiconductor memory device when in the preset operation mode, is latched in the semiconductor memory device until the device is brought again into the preset operation mode.
REFERENCES:
patent: 4387423 (1983-06-01), King et al.
patent: 4402043 (1983-08-01), Guttag et al.
patent: 4496944 (1985-01-01), Collmeyer et al.
patent: 4680701 (1987-07-01), Cochran
"Nikkei Electronics" of Nikkei, McGraw Hill Corp., Feb. 11, 1985, pp. 219-229.
"Hitachi IC Memory Data Book", Sep. 1983, pp. 314-320.
Miyake Jun
Yamaguchi Yasunori
Bowler Alyssa H.
Hitachi , Ltd.
Moffitt James W.
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