Semiconductor memory device having an improved data transmission

Details Semiconductor memory device having an improved data transmission Semiconductor memory device having an improved data transmission

1993-12-22

1995-07-25

Popek, Joseph A.

Static information storage and retrieval

Read/write circuit

Including level shift or pull-up circuit

365190, G11C 700

Patent

active

054368642

ABSTRACT:
A semiconductor memory device having an improved data transmission circuit reduces voltage swing width of data to be transmitted from a plurality of memory cells to an output buffer, so as to improve data reading speed. To do this, the semiconductor memory device has the plurality of memory cells for storing data, true and complementary data transmission lines for transmitting true and complementary data read from the plurality of memory cells to the output buffer, a first voltage source for supplying a first voltage level to the true and complementary data transmission lines, a first level shifter connected between true data transmission line and a second voltage source generating a second voltage level for shifting a first voltage level of true data transmission line to a third voltage level by true data of a predetermined logic value supplied from the plurality of memory cells, and a second level shifter connected between the complementary data transmission line and the second voltage source for shifting a first voltage level of complementary data transmission line to a third voltage level by complementary data of a predetermined logic value supplied from the plurality of memory cells.

REFERENCES:
patent: 4618785 (1986-10-01), Van Tran
patent: 4791613 (1988-12-01), Hardee
patent: 4866674 (1989-09-01), ran
patent: 4954992 (1990-09-01), Kumanoya et al.
patent: 4961168 (1990-10-01), Tran

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