Semiconductor memory device having an ECC circuit

Details Semiconductor memory device having an ECC circuit Semiconductor memory device having an ECC circuit

1998-11-12

2001-04-17

Decady, Albert (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Memory testing

C714S766000, C714S805000, C365S201000, C365S200000

Reexamination Certificate

active

06219807

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor memory device having an error checking and correcting (hereinafter abbreviated as ECC) circuit for correcting data error caused by a memory cell defect.
FIG. 4
is a schematic diagram illustrating a conventional example of an ECC code generation circuit.
For checking and correcting a one-bit error in 32-bit data, an ECC code of six bits is necessary. In the conventional example of
FIG. 4
, each bit (outputted from each of output terminals O
0
to O
5
of
FIG. 4
) of the ECC code is so generated as to have XOR (eXclusive OR) logic of each different combination of 14 bits (indicated by circles depicted on horizontal lines each connected to respective one of the output terminals O
0
to O
5
through a symbol of an XOR gate) of the 32-bit data inputted from input terminals D
00
to D
31
.
FIG. 5
is a schematic diagram illustrating data writing/reading of a conventional semiconductor memory device having an ECC circuit making use of the ECC code generation circuit of FIG.
4
.
When input data D[
31
:
0
] of 32 bits are supplied to be written in a memory-cell array
52
, an ECC code O[
5
:
0
] of 6 bits is generated by an ECC code generation circuit
51
from the input data D[
31
:
0
] as above described in connection with FIG.
4
.
The input data D[
31
:
0
] of 32 bits are written in the memory-cell array
52
being divided into four addresses
4
n,
4
n+1,
4
n+2 and
4
n+3 (n=0, 1, 2, . . . ) 8 bits by 8 bits. That is, when n=0, for example, first 8 bits D[
7
:
0
] of the input data are written in memory cells of an address
0
of user areas of bit-columns BIT
0
to BIT
7
. In the same way, second, third and fourth 8 bits D[
15
:
8
], D[
23
:
16
] and D[
31
:
24
] are written in memory cells of addresses
1
,
2
and
3
, respectively, of the user areas of the bit-columns BIT
0
to BIT
7
.
In parallel with the input data D[
31
:
0
] of 32 bits, the ECC code O[
5
:
0
] of 6 bits generated from the input data D[
31
:
0
] is written in memory cells of an address
4
n of ECC areas of the bit-columns BIT
0
to BIT
5
(the bit-columns BIT
6
and BIT
7
have no ECC area). That is, first to sixth bits of the ECC code O[
5
:
0
] are written in memory cells of an address
0
of ECC areas of the bit-columns BIT
0
to BIT
5
when n=0, or address
4
when n=1, respectively.
Thus, input data of 32 bits and their ECC code of 6 bits are written in the memory-cell array
52
, 38 bits by 38 bits, by incrementing n when the input data are to be written sequentially, and four sets of 38-bit data are written in each word-line of the memory-cell array
52
, in the conventional examples of FIG.
5
.
When data are read out from the memory-cell array
52
, user area data RD[
31
:
0
] of 32 bits from four addresses
4
n,
4
n+1,
4
n+2 and
4
n+3 of the user areas of bit-columns BIT
0
to BIT
7
and ECC area data RO[
5
:
0
] of 6 bits from the corresponding address
4
n of ECC areas of the bit-columns BIT
0
to BIT
5
are read out in parallel and supplied to an error correcting circuit
53
. The error correcting circuit
53
reproduces output data DO[
31
:
0
] of 32 bits having the same logic with the input data D[
31
:
0
] making use of the ECC area data RO[
5
:
0
] even if there is one-bit error in the 38 bits of the user area data RD[
31
:
0
] and the ECC area data RO[
5
:
0
] read out from the memory-cell array
52
.
Now, product inspection of memory-cell arrays is described.
Before shipping memory-cell arrays, product inspection is performed for checking if there is any defect, such as a bit interference defect, in memory-cell arrays to be shipped. Checker data writing and reading is a method used for the product inspection.
FIG. 6
is a schematic diagram illustrating the checker data written in a user area of one (BIT
0
, for example) of the bit-columns BIT
0
to BIT
5
(no ECC area is provided in the bit-columns BIT
6
and BIT
7
) of the memory-cell array
52
of FIG.
5
. In the checker data writing, input data are given to compose a checkerboard pattern in the memory-cell array, so that logic ‘0’ and logic ‘1’ are written alternately both in horizontal and vertical, to be read out and checked at once making use of a hardware logic.
FIG. 7
is a schematic diagram illustrating bit-pattern examples of the checker data.
For writing the checkerboard pattern as illustrated in
FIG. 6
in the user areas of bit-columns BIT
0
to BIT
7
, input data D[
31
:
0
] of 32 bits having a bit-pattern BP
11
of
FIG. 7
are written four times on a word-line #
1
of
FIG. 5
by incrementing n from 0 to 3, and then, input data D[
31
:
0
] having another bit-pattern BP
12
of
FIG. 7
are written four times on a next word-line #
2
by incrementing from 4 to 7. By repeating these procedures, the checkerboard pattern is written in the user area of each of the bit-columns BIT
0
to BIT
7
.
However, in the ECC areas of the bit-columns BIT
0
to BIT
5
of the memory-cell array
52
of
FIG. 5
, the memory cells do not compose the checkerboard pattern, when checker data having the bit-patterns BP
11
and BP
12
of
FIG. 7
are written in the user areas.
When the ECC code O[
5
:
1
] is generated from XORs of 14 bits of the input data D[
31
:
0
] by the ECC code generation circuit
51
having the configuration of
FIG. 4
, the ECC code O[
5
:
1
] becomes ‘100001’ for both of the bit-patterns BP
11
and BP
12
. Therefore, logic of every memory cell in the ECC area becomes ‘1’ in the bit-column BIT
0
and bit-column BIT
5
, as shown in
FIG. 6
, and becomes ‘0’ in the bit-columns BIT
1
to BIT
4
, disabling memory cells in the ECC areas to be checked at the same time with memory cells in the user areas.
Hence, in the conventional semiconductor memory device having the ECC circuit, the product inspection by checker data writing and reading should be performed two times, once for the user areas and once for the ECC areas making use of special checker data to compose the checkerboard pattern in the ECC areas.
The two times checker-data inspection makes high the cost of the product inspection.
Furthermore, it degrades the yield rate of the semiconductor memory device. In the semiconductor memory device having the ECC circuit, one-bit error in the 32-bit data can be corrected automatically. In other words, even if there is one-bit defect in 38 memory cells of an address unit, that is, addresses
4
n,
4
n+1,
4
n+2 and
4
n+3 of the user areas of the bit-columns BIT
0
to BIT
7
and an address
4
n of the ECC areas of the bit-columns BIT
0
to BIT
5
of a semiconductor memory device, it call be used without problem. However, the checker-data inspection should be performed separately for the user areas and the ECC areas, in the conventional semiconductor memory device having the ECC circuit. Therefore, when one-bit defect is found in 6 bets of an address of the ECC areas in the checker-data inspection, the semiconductor memory device should have been rejected.
These are problems of the conventional semiconductor memory device having the ECC circuit.
SUMMARY OF THE INVENTION
Therefore, a primary object of the present invention is to provide a semiconductor memory device having an ECC circuit whereof checker-data inspection of memory cells in the user areas and the ECC areas can be performed at once, for improving productivity of the semiconductor memory device by reducing the inspection time and avoiding degradation of the yield rate because of unnecessary rejection.
In order to achieve the object, an ECC code generation circuit generates the ECC code of six bits whereof logic of each bit has XOR logic of each of six different combinations of 15 bits of the data set of 32 bits in a semiconductor memory device of the invention, and addresses

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