Semiconductor memory device having an array of memory cells...

Details Semiconductor memory device having an array of memory cells... Semiconductor memory device having an array of memory cells...

1998-02-13

2001-11-27

Chaudhuri, Olik (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S310000, C257S311000, C438S240000, C438S003000

Reexamination Certificate

active

06323510

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device and more particularly, to a semiconductor memory device each memory cell of which is comprised of a select transistor and a ferroelectric storage capacitor for electric-charge storing.
2. Description of the Prior Art
FIG. 1
shows a memory cell structure of a conventional semiconductor memory device of this sort, which is disclosed in the Japanese Non-Examined Patent Publication No. 4-144282 published in May 1992.
This conventional semiconductor memory device has a lot of memory cells
800
with a same structure, which are arranged in a matrix array. However, only two ones of the cells
800
are shown in
FIG. 1
for the sake of simplification of description.
As shown in
FIG. 1
, each of the memory cells
800
has a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET)
600
serving as a select transistor and a storage capacitor
700
for electric-charge storing.
The MOSFET
600
is formed by a source region
107
s
and a drain region
107
d
formed in a semiconductor substrate (not shown), and a common gate electrode
151
formed over the substrate through a gate oxide layer (not shown). The common gate electrode
151
serves as word lines electrically connecting the corresponding gate electrodes
151
to one another.
The drain region
107
d
is electrically connected to an overlying bit line
152
through a contact hole
153
.
The source region
107
s
is electrically connected to an overlying wiring layer
104
through a contact hole
103
. The wiring layer
104
is electrically connected to an underlying upper electrode
102
of the storage capacitor
700
. Thus, the source region
107
s
is electrically connected to the overlying upper electrode
102
of the storage capacitor
700
.
The storage capacitor
700
has a square-shaped ferroelectric
101
sandwiched by a strip-shaped, common lower electrode
109
and the square-shaped upper electrode
102
. The common lower electrode
109
extends along a word line
151
perpendicular to the bit line
1152
. The ferroelectric
101
has a slightly wider area than the upper electrode
102
. The ferroelectric
101
has a same width as the lower electrode
109
.
The lower electrode
109
is electrically connected to an overlying wiring layer
114
through a contact hole
112
. The wiring layer
114
is electrically connected to an overlying wiring layer
154
through a contact hole
115
. Thus, the lower electrode
109
is electrically connected to the wiring layer
154
. The wiring layer
154
extends along the lower electrode
109
and is overlapped therewith.
As described above, in the conventional memory cell structure shown in
FIG. 1
, the common lower electrode
109
is commonly used by the memory cells
800
arranged along the word line
151
.
FIGS. 2A
to
2
C show a memory cell layout of another conventional semiconductor memory device, where a lot of memory cells
800
with substantially the same structure as shown in
FIG. 1
are arranged in a matrix array.
FIG. 3
shows a cross section along the line III—III in FIG.
2
A.
As clearly shown in
FIGS. 2B and 3
, source regions
107
s
and drain regions
107
d
of MOSFETs
600
are formed in a semiconductor substrate
110
. Gates electrodes
151
, which serve as word lines, are arranged over the substrate
110
through corresponding gate oxide layers
108
a.
Each pair of the source and drain regions
107
s
and
107
d
are located at each side of a corresponding one of the gate electrodes
151
.
Bit lines
152
are formed on an interlayer insulating layer
108
b
covering the gate electrodes or word lines
151
. The bit lines
152
are contacted with and electrically connected to the corresponding drain regions
197
d
through corresponding contact holes
153
penetrating the interlayer insulating layer
108
b.
Strip-shaped lower electrodes
109
of storage capacitors
700
are formed on an interlayer insulating layer
108
c
covering the bit lines
152
. The lower electrodes
109
extend along the word lines
151
. Square-shaped ferroelectrics
101
of the storage capacitors
700
are formed on the corresponding square-shaped lower electrodes
109
. Square-shape upper electrodes
102
of the storage capacitors
700
are formed on the corresponding ferroelectrics
101
.
Each of the ferroelectrics
101
has a same area as a corresponding one of the lower electrodes
109
. In other words, each of the ferroelectrics
101
is entirely overlapped with a corresponding one of the lower electrodes
109
. Each of the upper electrodes
102
has a narrower area than a corresponding one of the lower electrodes
109
. In other words, each of the upper electrodes
102
is included in a corresponding one of the ferroelectrics
101
The storage capacitors
700
are located just over the corresponding drain regions
107
d
or just over the positions between the adjoining source regions
107
s.
Wiring layers
104
are formed on an interlayer insulating layer
108
d
covering the storage capacitors
700
. The wiring layers
104
are contacted with and electrically connected to the upper electrodes
102
through corresponding square-shaped contact holes
105
penetrating the interlayer insulating layer
108
d.
The wiring layers
104
are further contacted with and electrically connected to the source regions
107
s
through corresponding square-shaped contact holes
103
penetrating the interlayer insulating layers
108
d,
108
c,
and
108
b.
The wiring layers
104
are covered with an interlayer insulating layer
108
e.
Here, it is supposed that one side of the square-shaped upper electrode
102
has a length of a, the side length a of the upper electrode
102
and the width of the lower electrode
109
has a difference of d, the opposing ends of the lower electrode
109
and the corresponding contact hole
105
has a distance of x, one side of the square-shaped contact hole
105
has a length of c, and the opposing ends of the adjoining upper electrodes
109
has a distance of y. Then, the chip area Sc of each memory cell
800
is expressed by the following expression (1).
Sc
=
(
d
/
2
+
a
+
d
/
2
+
x
+
c
+
x
)
·
(
a
+
y
)
=
(
a
+
d
+
c
+
2
⁢
x
)
·
(
a
+
y
)
(
1
)
If the difference d is increased to (d+&Dgr;d), the chip area Sc is expressed as the following expression (2).
Sc=
(
a+d+&Dgr;d+c+
2
x
)·(
a+y
)  (2)
Therefore, the chip area Sc is increased by
&Dgr;
d·
(
a+y
)·
For example, if the size difference d is set as a small value of 0.2 &mgr;m, the remanent polarization of the ferroelectric layers
101
tends to degrade to approximately 60% of its inherent value after the formation processes of the storage capacitors
700
. This is because the side ends of ferroelectrics
101
extending in parallel to the word lines
151
are damaged due to the etching or milling action during the patterning process for the ferroelectrics
101
.
Therefore, to prevent this damage, the size difference d needs to be set as approximately 1.0 &mgr;m or more. In this case, however, this large value of the difference d will cause a problem that the chip area Sc of the memory cell
800
is increased. This problem prevents higher integration of the memory cells
800
.
In the case where the size difference d is set as 0.2 &mgr;m, if a=2.0 &mgr;m, x=0.6 &mgr;m, c=0.9 &mgr;m, and y=2.0 &mgr;m, the chip area Sc is given from the above expression (1) as follows.
(2.0+0.2+0.9+2×0.6)·(2.0+2.0)=17.2 &mgr;m
2
On the other hand, when only the size difference d is increased to 1.0 &mgr;m, the chip area Sc is given as follows.
(2.0+1.0+0.9+2×0.6)·(2.0+2.0)=20.4 &mgr;m
2
Therefore, by increasing the size difference d by 0.8 &mgr;m, the chip area Sc is increased by 3.2 &mgr;m
2
(which is equal to approximately 19% of 17.2 &mgr;m
2
).
Next, the reliability degradation due to parasitic capacitance is explained below.
In the conventi

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