Semiconductor memory device having alternatively operated equali

Details Semiconductor memory device having alternatively operated equali Semiconductor memory device having alternatively operated equali

1991-07-17

1993-10-19

Grimm, Siegfried H.

Static information storage and retrieval

Read/write circuit

Including reference or bias voltage generator

36518911, 365203, 365218, G11C 11407

Patent

active

052552233

ABSTRACT:
In a semiconductor memory device comprising memory cells connected at the intersections of pairs of bit lines and word lines, sense amplifiers activated by the potentials on common nodes to amplify the potential differences between the respective pairs of the bit lines, an equalizing circuit activated by an equalizing signal to apply the potential on a power supply node to the pairs of bit lines, and a reference potential supplying circuit for generating a reference potential and supplying the reference potential to the power supply node through a switching circuit, a circuit is provided to block the application of the reference potential to the bit lines and the sense amplifier common nodes and to apply a negative potential to the bit lines. The word lines are held at the ground level, so the physical "0" is written into all the memory cells simultaneously.

REFERENCES:
patent: 4656608 (1987-04-01), Aoyama
patent: 4780850 (1988-10-01), Miyamoto et al.
patent: 5091889 (1992-02-01), Hamano et al.

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