Semiconductor memory device having altered clock frequency...

Details Semiconductor memory device having altered clock frequency... Semiconductor memory device having altered clock frequency...

2001-09-05

2002-12-17

Lam, David (Department: 2818)

Static information storage and retrieval

Addressing

Sync/clocking

C365S189050, C365S230080

Reexamination Certificate

active

06496445

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a memory device and to a memory module and system, and more particularly, the present invention relates to a semiconductor memory device which generates internal clock signals and to a memory module and system having the same.
2. Description of the Related Art
The increasing demand for computer systems capable of processing large amounts of data at high speeds has resulted in the continued development of highly efficient micro-controllers or central processing units (CPUs) which tend to operate at higher and higher system clock frequencies. The use of higher system clock frequencies requires, among other things, an increase in the data capacity and transmission speed of a data memory interfacing with the CPU. In other words, the memory must be configured to operate in synchronization with higher-frequency system clock signals.
FIG. 1
is a diagram illustrating a memory controller
110
and a memory module
120
of a CPU system board
100
. The memory controller
110
transfers a clock signal CLK, an address signal ADDR, a command signal CMD and data DATA to the memory module
120
through a CLOCK BUS line, an ADDRESS BUS line, a COMMAND BUS line and a DATA BUS, respectively. The memory module
120
includes a plurality of memory chips (e.g.,
8
memory chips)
101
,
102
, . . . ,
108
embedded therein, each of which is connected to the CLOCK BUS line, the ADDRESS BUS line, the COMMAND BUS line and the DATA BUS as shown.
The clock signal CLK is supplied to the memory chips
101
,
102
, . . . ,
108
to control the operation thereof. Also, in the case where the memory chips
101
,
102
, . . . ,
108
are synchronous DRAM chips, the command signal CMD, the address signal ADDR and the data DATA are synchronized with edges of the clock signal CLK.
As shown in
FIG. 1
, the data DATA is input to/output from the memory chips
101
,
102
, . . . ,
108
via the DATA BUS through independent multi-bit data lines connected to the respective memory chips
101
,
102
, . . . ,
108
. Thus, the load of each data line is one memory chip. On the contrary, the address signal ADDR and the command signal CMD are commonly supplied to the memory chips
101
,
102
, . . . ,
108
. As such, the ADDRESS BUS and COMMAND BUS lines are each subjected to the combined load of all of the memory chips
101
,
102
, . . . ,
108
.
As suggested previously, high speed CPUs are attended by high frequency clock signals CLK. Generally, the data DATA of the DATA BUS may be operated at such high frequencies since the load of each data line is relatively small (one memory chip). On the other hand, relatively high multi-memory chip loads of the ADDRESS BUS and COMMAND BUS lines can prevent high frequency operation of these lines. The loads of the ADDRESS BUS and COMMAND BUS lines can therefore limit the effective operating speed of the memory to less than the system clock speed.
FIG. 2
is a block diagram of a conventional memory module
120
. A plurality of bus lines connected to a microprocessor (not shown) or a memory controller (not shown), typically a clock bus, an address bus and a command bus, are arranged on a system board. The memory module
100
includes a plurality of memory chips
101
,
102
, . . . ,
106
, a phase locked loop (PLL)
107
and a register
108
.
The PLL
107
receives a clock signal CLK loaded on the clock bus line and generates a plurality of internal clock signals ICLK
0
, ICLK
1
, . . . , ICLK
6
. It is assumed here that the plurality of internal clock signals ICLK
0
, ICLK
1
, . . . , ICLK
6
are ideal signals having the same slew rate and duty cycle without skew. Since the plurality of internal clock signals ICLK
0
, ICLK
1
, . . . , ICLK
6
are synchronized in phase with the clock signal CLK, they have the same frequency as that of the clock signal CLK. The internal clock signal ICLK
0
is supplied to the register
108
, and the internal clock signals ICLK
1
, ICLK
2
, . . . , ICLK
6
are supplied to the memory chips
101
,
102
, . . . ,
106
. In
FIG. 2
, one clock signal is connected to one memory chip. However, in actual applications, the number of corresponding memory chips for one clock signal may vary. The register
108
receives the address signal ADDR and the command signal CMD in response to the internal clock signal and transmits the received signals to the respective memory chips
101
,
102
, . . . ,
106
.
Since the memory module
120
receives only one clock signal CLK and generates a plurality of internal clock signals ICLK
1
, ICLK
2
, . . . , ICLK
6
, the frequencies of the internal clock signals ICLK
1
, ICLK
2
, . . . , ICLK
6
increase as the frequency of the clock signal CLK increases in a high-performance system. Since the memory chips
101
,
102
, . . . ,
106
, which receive the internal clock signals ICLK
1
, ICLK
2
, . . . , ICLK
6
and operate responsive thereto, may be constructed of devices suitable for high-frequency operation, no problems arise from their operation. However, it is doubtful whether the register
108
can function to receive the address signal ADDR and the command signal CMD at a timing corresponding to the frequency of the internal clock signal ICLK
0
, that is, the high frequency clock signal CLK, and to then transmit the received signals to the memory chips
101
,
102
, . . . ,
106
, in synchronization with the same high frequency clock signal CLK. As such, the operating characteristics of the register
108
may also limit the effective operating speed of the memory to less than the system clock speed.
SUMMARY OF THE INVENTION
It is an objective of the present invention to provide a semiconductor memory device which can utilize operable frequencies of an address signal and a command signal even if the frequency of a system clock signal is increased.
It is another objective of the present invention to provide a system having a memory device and a memory module which can utilize a clock signal having a sufficiently low frequency which is suitable for the operation of a register even if the frequency of a system clock signal is increased.
According to one aspect of the present invention, a semiconductor memory device includes a clock buffer which receives an external clock signal, and which outputs a first internal clock signal having a frequency which is lower than a frequency of the external clock signal and a second internal clock signal having a frequency which is the same as the frequency of the external clock signal; an address buffer which receives an address signal at a timing of the first internal clock signal; and a data buffer which inputs/outputs data at a timing of the second internal clock signal.
According to another aspect of the present invention, a semiconductor memory device includes a clock buffer which receives an external clock signal and a control signal, and which is responsive to the control signal to output a first internal clock signal having a frequency which is lower than a frequency of the external clock signal and a second internal clock signal having a frequency which is the same as the frequency of the external clock signal; a controller which outputs the control signal designating the frequency of the first internal clock signal relative to the frequency of the second internal clock signal; an address buffer which receives an address signal at a timing of the first internal clock signal; a command buffer which receives a command signal at a timing of the first internal clock signal; and a data buffer which inputs/outputs data at a timing of the second internal clock signal.
According to still another aspect of the present invention, a semiconductor memory system includes a memory controller; a plurality of bus lines which are connected to the memory controller and which transfer an address signal, a command signal and data; and a memory module having a plurality of semiconductor memory devices connected to the memory controller through the plurality of bus lines, wherein each of the semiconductor memory device

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