Static information storage and retrieval – Read/write circuit – Bad bit
Patent
1993-09-20
1995-05-09
Popek, Joseph A.
Static information storage and retrieval
Read/write circuit
Bad bit
3652257, 3652335, 327 1, 327526, 326 10, 326106, G11C 2900
Patent
active
054146593
ABSTRACT:
A plurality of address transition detecting circuits incorporated in a semiconductor memory device monitors address bits to see whether or not at least one address bits is changed in logic level for producing an address transition signal from the output signals of the respective address transition detecting circuits, and a plurality of charging transistors coupled in parallel between a power voltage line and a decoding line are respectively gated by the output signals of the address transition detecting circuits for charging the decoding line so that a decoding circuit quickly determines whether or not the stored address is matched with the address represented by the address bits for replacing a defective row of regular memory cells with a row of redundant memory cells.
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patent: 4689494 (1987-08-01), Chen
patent: 4817056 (1989-03-01), Furutani
patent: 4922134 (1990-05-01), Hoffmann
patent: 5239511 (1993-08-01), Oh
patent: 5258953 (1993-11-01), Tsujimoto
patent: 5282165 (1994-01-01), Mijake
patent: 5289417 (1994-02-01), Ooishi
patent: 5293339 (1994-03-01), Suzuki
Mai Son
NEC Corporation
Popek Joseph A.
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